IOSR Journal of Electronics and Communication Engineering(IOSR-JECE)

Volume 5 - Issue 3

Paper Type : Research Paper
Title : Nonlinear Commanding Transform Algorithm for Peak -To-Average Power Ratio Reduction Technique of OFDM Signal
Country : India
Authors : Mrs. Sharda S. Mandlik, Mr. Shrish L. Kotgire
: 10.9790/2834-0530106      logo

Abstract: Orthogonal Frequency Division Multiplexing (OFDM) is digital multicarrier Modulation access system for high data rate transfer .But it has high PEAK To Average Power Ratio which increases complexity of A/D Converter and D/A Converters and lowers the efficiency of power amplifiers. In this paper Repeated Clipping and Filtering (RCF) distortion PAPR Reduction technique of an OFDM signal which is existing technique for reducing high Peak –to –Average Power of an OFDM signal. The basic idea of Repeated Clipping and Filtering(RCF) algorithm is to generate the anti-peak signal for Peak-to-Average Power Ratio (PAPR) reduction by projecting the clipping in-band noise into the feasible extension area while removing the Out-of-Band Interference (OBI), also called as Out-of-Band Distortion with filtering [3]. The Clipping and filtering method suffers from the three major problems like in-band distortion, out-of-band radiation & peak re-growth after digital to analog conversion [24.

Keywords - Orthogonal Frequency Division Multiplexing (OFDM), Peak-to-Average Power Ratio (PAPR), Nonlinear Companding Transform (NCT), Repeated Clipping and filtering (RCF) algorithm Bit Error Rate (BER).

[1] Armstrong. Peak-to-average power reduct ion for OFDM by repeated clipping and frequency domain filtering. Electronics letters, Vol.38, No.5, pp.246-247, Feb.2002

[2] IEEEStandard, 802.11a.Part11: Wireless LAN medium access control (MAC)and physical (PHY)specifications.IEEE,1999

[3] Kitaek Bae, Jeffrey G. Andrews, Edward J. Powers, "Adaptive Active Constellation Extension Algorithm for Peak-to-Average Ratio Reduction in OFDM", IEEE Communications Letters, Vol. 14, no. 1, January 2010.

[4] Tao Jiang, Yang Yang, Yong-Hua Song, "Exponential Companding Technique for PAPR Reduction in OFDM Systems", IEEE Transactions on Broadcasting, vol. 51, no. 2, June 2005.

[5] Jun Hou, Jianhua Ge, Dewei Zhai, and Jing Li, "Peak-to-Average Power Ratio Reduction of OFDM Signals With Nonlinear Companding Scheme", IEEE Transactions on Broadcasting, vol. 56, no. 2, June 2010.

[6] Stephane Y. Le Goff, Samer S. Al-Samahi, Boon Kien Khoo, Charalampos C. Tsimenidis, and Bayan S. Sharif, "Selected Mapping without Side Information for PAPR Reduction in OFDM" , IEEE Transactions on Wireless Communications, vol. 8, no. 7, July 2010 [7] Cristina Ciochina and Hikmet Sari,"A Review of OFDMA and Single-Carrier FDMA"2010,Europian Wireless Conference

[8] Bai, W., Xiao, Y., Li, S. "The peak-to-average power ratio distribution of LFDMA signals"2009 4th International Conference on Communications and Networking in China, CHINACOM 2009 , art. no. 5339758, pp. 945-948

[9] Tao Jiang, " An Overview: Peak –to-Average Power Ratio Reduction Techniques for OFDM signals" IEEE Transactions on broadcasting, vol.54, No.2, June 2008

[9] T. Jiang, W. Xiang, H. H. Chen, and Q. Ni, " Multicast broadcasting services support in OFDMA-based WIMAX systems", IEEE Communications Magazine, vol. 45, no. 8, pp. 7886, Aug.2007

[10] on-multiplexing.

Paper Type : Research Paper
Title : FPGA Implementation of MB-OFDM Using Biorthogonal Encoder
Country : India
Authors : Palaniappan.T, Veluchamy.S
: 10.9790/2834-0530714      logo

Abstract: UWB is a high data rate, short range technology .It transmits the information over a minimum bandwidth of 500 MHZ. Modern UWB systems use Modulation techniques such as OFDM (Orthogonal Frequency Division Multiplexing). The MB-OFDM proposal is selected for UWB system model. Multiband OFDM (MB-OFDM) is a short-range wireless technology that permits data transfers at very high rates, between 53.3 and 480 Mbps. For the requirement of Multiband-OFDM system, the processor should work on a few hundred MHz, which makes it difficult to implement. And since the system targets for the wireless portable devices, small area and low power consumption are also imperative. Therefore a 8-way parallel architecture based on bi-orthogonal encoder is proposed in this paper. In order to satisfy the performance requirement, the proposed architecture reduces the power consumption and utilizes more bandwidth and also detects and corrects both random and burst errors. It is used for multiuser transmission scheme and also works at high speed. The detailed analysis shows that the proposed technique could reduce the gate count by 32.47% on average. With 0.18-μm CMOS process, clock rate of the entire baseband modem was about 66 MHz and BER was 5.57e-138.

Index terms- multi-band orthogonal frequency division multiplexing (MB-OFDM), parallel architecture, ultra wide band (UWB), resource optimization.

[1] SeokJoong Hwang, Student Member, IEEE, Youngsun Han, SeonWook Kim," Resource efficient implementation of low power Mb-OFDMphy baseband modem with highly Parallel architecture", IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 20, no. 7, pp.1248-1261,july 2012.
[2] C.-H. Shin, S. Choi, H. Lee, and J.-K. Pack, "A design and performance of 4-Parallel MB-OFDM UWB receiver," IEICE Trans. Commun., vol.E90-B, no. 3, pp. 672–675, Mar. 2007.
[3] W. H. Wu, Y. W. Wu, and H. P. Ma, "A 480 Mbps MB-OFDM-basedUWB baseband inner transceiver," in Proc. IEEE Asia Pacific Conf.Circuits Syst. (APCCAS), 2008, pp. 164–167.
[4] A. Chandrakasan and R. Brodersen, "Minimizing power consumptionin digital CMOS circuits," Proc. IEEE, vol. 83, no. 4, pp. 498–523,Apr. 1995.
[5] A. Safarian, A. Yazdi, and P. Heydari, "Design and analysis of an ultrawide-band distributed CMOS mixer," IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 13, no. 5, pp. 618–629, May 2005.
[6] C. Cheng and K. K. Parhi, "High-throughput VLSI architecture for FFT computation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 10,pp. 863–867, Oct. 2007.
[7] A. Chindapol and J. A. Ritcey, "Design, analysis, and performance evaluation for BICM-ID with square QAM constellations in Rayleigh fading channels," IEEE J. Select. Areas Commun., vol. 19, no. 5, pp.944–957, May 2001.
[8] A. Troya, K. Maharatna, M. Krstic, E. Grass, U. Jagdhold, and R.Kraemer, "Efficient inner receiver design for OFDM-based WLAN systems: Algorithm and architecture," IEEE Trans. Wirel. Commun.,
[9] vol. 6, no. 4, pp. 1374–1385, Apr. 2007.
[10] A. Batra, J. Balakrishnan, G. R. Aiello, J. R. Foerster, and A. Dabak, "Design of a multiband OFDM system for realistic UWB channel environments,"IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, pp.2123–2138, Sep. 2004.

Paper Type : Research Paper
Title : A New Class of Binary Zero Correlation Zone Sequence Sets
Country : France
Authors : B. Fassi, A. Djebbari, Taleb-Ahmed. A, And I. Dayoub
: 10.9790/2834-0531519      logo

Abstract: This paper proposes a new class of binary zero correlation zone (ZCZ) sequence sets, in which the periodic correlation functions of the proposed sequence set is zero for the phase shifts within the zero-correlation zone. It is shown that the proposed zero correlation zone sequence set can reach the upper bound on the ZCZ codes.

Keywords- Sequence design, theoretical upper bound, zero correlation zone (ZCZ) sequences.

[1] P. Z. Fan, N. Suehiro, N. Kuroyanagi and X. M. Deng, Class of binary sequences with zero correlation zone, IEE Electronic Letters, 35(10), 1999, 777-779.
[2] H. Torii, M. Nakamura, N. Suehiro, A new class of zero-correlation zone sequence, IEEE. Trans. Inf. Theory, 50(3), 2004, 559-565.
[3] H. Torri, M. Nakamura, N. Suehiro, Enhancement of ZCZ sequence set construction procedure, Proc. IWSDA05, 2005, 67-72.
[4] T. Hayashi, A class of zero-correlation zone sequence set using a perfect sequence, IEEE Signal ProcessingLetters, 16(4),2009, 331-334.
[5] Kai Liu, ChengqianXu Gang Li, Binary zero correlation zone sequence pair set constructed from difference set pairs, Proceedings of International Conference on Networks Security, Wireless Communications and Trusted Computing (NSWCTC'09),2, 2009, 543-546.
[6] T. Maeda, S. Kanemoto, T. Hayashi, A Novel Class of Binary Zero-Correlation Zone Sequence Sets, N°978-1-4244-6890-©2010 IEEE, TENCON 2010.
[7] S. Renghui, Z. Xiaoqun, Li. Lizhi, Research on Construction Method of ZCZ Sequence Pairs Set, Journal of Convergence Information Technology, 6(1). January 2011.
[8] A. Rathinakumar and A.K. Chaturvedi, Mutually orthogonal sets of ZCZ sequences, ELECTRONICS LETTERS,40 (18),2004.
[9] T. Hayashi, Limits of the Correlation Function of a Class of Binary Zero-correlation-zone Sequences,, June 6, 2002.

Paper Type : Research Paper
Title : An Area and Delay Efficient Csla Architecture
Country : India
Authors : J. Pravin adlin , C. Palaniappan
: 10.9790/2834-0532025      logo

Abstract: Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Experimental results are compared and the result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power.

Index Terms- area efficient, CSLA, low power and BEC

[1] Anitha Kumari R D, Nayana N D-(2011), "Low power and Area Efficient Carry Select Adder", National Conference on Electronics, Communication and Signal Processing, NCECS.
[2] 2. Bedrij O.J-(1962), "Carry-select adder," IRE Trans. Electron. Comput., pp.340–344.
[3] Ceiang T Y and Hsiao M J, (Oct. 1998) "Carry-select adder using single ripple carry adder," Electron. Lett., vol. 34, no. 22, pp. 2101–2103,.
[4] Jeong .W and Roy .K(2003), "Robust high-performance low power adder", Proc. of the Asia and South Pacific Design Automation Conference, pp. 503-506.
[5] He Y, Chang C H, and Gu J(2005), "An area efficient 64-bit square root carry select adder for low power applications," in Proc. IEEE Int. Symp. Circuits Syst., vol. 4, pp. 4082–4085.
[6] Hosseinghadiry M, Mohammadi H and Nadisenejani M,(2009) '' Two New Low Power High Performance Full Adders with Minimum Gates", World Academy of Science, Engineering and Technology 52 .
[7] KeivanNavi and NedaKhandel, (2008)"The Design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function", European Journal of Scientific Research, ISSN 1450-216X Vol.23 No.4 pp.626-638.
[8] Kim Y and Kim L S(May 2001), "64-bit carry-select adder with reduced area", Electron.Lett., vol. 37, no. 10, pp. 614–615,.
[9] Manoj Kumar, Sandeep K. Arya and SujataPandey,( December 2011) "Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate", International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4,.
[10] Massimo Alioto and Gaetano Palumbo, (August 28-31, 2001,)"Optimized Design of Carry-Bypass Adders", ECCTD'01 - European Conference on Circuit Theory and Design, Espoo, Finland.

Paper Type : Research Paper
Title : Comparative Study of OFDM and CDMA Technique
Country : India
Authors : Lalit Singh GariA, Amit Shah, Deepesh Rawat
: 10.9790/2834-0532630      logo

Abstract: Orthogonal frequency division multiplex (OFDM) modulation is being used more and more in telecommunication both in wired and wireless. This modulation technique has several advantages, reason for its increasing usage in communication. OFDM can provide high data rates, it can be implemented easily, it is spectrally efficient and with sufficient robustness to channel imperfections. On the other hand most third generation mobile phone systems are using Code Division Multiple Access (CDMA) as their modulation technique. For this reason, CDMA is also investigating so that the performance of both CDMA and OFDM can be compared. It is found that OFDM performs extremely well when compared with CDMA, and provide very high tolerance to multipath delay spread, channel noise, and peak power clipping. In addition to this it provides a high spectral efficiency The noise performance of OFDM is found to depend solely on the modulation technique used for modulating each carrier of the signal. The OFDM signal performance is found to be the same as for a single carrier system, using the same modulation technique and can provide large data rates with sufficient robustness to radio channel impairments The minimum signal to noise ratio (SNR) required for BPSK was ~7 dB, where as it was ~12 dB for QPSK and ~25 dB for 16PSK. CDMA was found to perform poorly in a single cellular system, with each cell only allowing 7-16 simultaneous users in a cell, compared with 128 for OFDM.1.25 MHz bandwidth and 19.5 kbps user data rate was used for it. This low cell capacity of CDMA was attributed to the use of non-orthogonal codes used in the reverse transmission link, leading to a high level of inter-user interference.


[1] Y. Mostofi and D. C. Cox, "Mathematical analysis of the impact of timing synchronization errors on the performance of an OFDM
system," IEEE Trans. Commun., vol. 54, no. 2, pp. 226–230, Feb. 2006.
[2] A Brief History of OFDM /commentary/wimax_weekly/sidebar-1-1-a-brief-history-of-ofdm
[3] Heiskala, Juha and Terry, John. OFDM Wireless LANs: A Theoretical and Practical Guide SAMS 2001]
[4] P. H.Moose, "A technique for orthogonal frequency division multiplexing frequency offset correction," IEEE Trans. Commun., vol.
42, no. 10, pp. 2908–2914, Oct. 1994.
[5] H. Steendam and M. Moeneclaey, "Analysis and optimization of the performance of OFDM on frequency-selective time-selective
fading channels," IEEE Trans. Commun., vol. 47, no. 12, pp. 1811–1819, Dec. 1999.
[6] Orlandos Grigoriadis "Ber Calculation Using Matlab Simulation For Ofdm Transmission", IMECS 2008, 19-21 March, 2008, Hong
[7]. J. D. Gibson, "The mobile communications handbook", CRC Press, pp. 366-368, 1996.
[8]. D. Whipple, "North American Cellular CDMA", Hewlett-Parkard Journal, pp. 90-97, December 1993.
[9] Edfors, O., Sandell, M., Van de Beek, J.-J., Landström, D., and Sjöberg, F., An Introduction to Orthogonal Frequency Division
Multiplexing, Luleå, Sweden: Luleå Tekniska Universitet, 1996, pp. 1–58.

Paper Type : Research Paper
Title : A New Method of Image Fusion Technique for Impulse Noise Removal in Digital Images using the quality Assessment in Spatial Domain
Country : India
Authors : Ajay kumar Beesetti, Dr.Rajyalakshmi Valluri, Minusha Songa
: 10.9790/2834-0533134      logo

Abstract: Due to advancement of technology, remote sensing plays very important role in satellite based communication. Satellite gives images in digital format. The digital images are corrupted by impulse noise due to errors generated in camera sensors, analog-to-digital conversion and communication channels. The noise density varies depending on various factors namely reflective surfaces, atmospheric variations, noisy communication channels etc. Impulse noise corruption is very common in digital images. Therefore it is necessary to remove impulse noise in-order to provide further processing such as edge detection, segmentation, pattern recognition etc. Filtering a noisy image, while preserving the image details is one of the most important issues in image processing. The images captured by different sensors, producing different impulse noisy images are considered and they undergoes iterative filtering algorithm, search for the noise-free pixels within a small neighborhood. These filtered images are combined to a single image called image fusion, which retains the important features of the images from individual sensors. In this paper, we introduce an image fusion technique for impulse noise reduction, where the fused image will combine the uncorrupted pixels of the filtered noisy images. The performance of the Image Fusion is evaluated by using a reference image quality metric, Structural similarity Index (SSIM), to estimate how well the important information in the de-noised images is represented by the fused image. Experimental results show that the fused image has more quality than other filtered images.

Keywords - Impulse Noise, Image fusion, Filtering, De-noised Image.

[1] Nikolaos Mitianoudis, Tania Stathaki, Pixel-based and Region-based Image Fusion schemes using ICA bases, Communications and Signal Processing group, Preprint submitted to Elsevier Science, 13th Dec 2007.

[2]. Reihard Berstein, "Adaptive nonlinear filters for simultaneous removal of different kinds of noise in images," IEEE Trans on circuits and systems, Vol.cas-34, no11, pp.127-1291, Nivember1987.

[3] A. HyvÄarinen, P. O. Hoyer, and E. Oja. Image denoising by sparse code shrinkage. In S. Haykin and B. Kosko, editors, Intelligent Signal Processing. IEEE Press, 2001.

[4] P. Hill, N. Canagarajah, and D. Bull. Image fusion using complex wavelets. In Proc.13th BritishMachineVisionConference, Cardi®, UK, 2002.

[5] James C. Church, Yixin Chen, and Stephen V. Rice , ―A Spatial Median Filter for Noise Removal in Digital Images―, 2008 IEEE. [6] M. Vett, erli and C. Herley, "Wavelets and filter banks: theory and design," IEEE Tram Signal Processing, vol. 40, pp. 2207-2232, September 1992.

[7] P. Burt and R. Lolczynski, "Enhanced image capture through fusion," in Proc. the Fourtt International Conference on Computer Vision, pp. 173- 182, 1993.

[8] Tao Chen, Kai-Kaung Ma and Li-Hui Chen, ―"Tri-state median filter for image Denoising", IEEE Transactions on Image Processing, Vol 8, no.12, pp.1834-1838, December 1999.
[9] S.Indu, Chaveli Ramesh, ― "A noise fading technique for images corrupted with impulse noise", Proceedings of ICCTA07,IEEE

Paper Type : Research Paper
Title : Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
Country : India
Authors : Ritam Dutta, Krishanu Mitra, Moumita Majumdar
: 10.9790/2834-0534248      logo

Abstract: In modern era of advanced VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital data converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) applications. This low power 8-bit flash Analog to Digital data converter comprises 255 comparators and one thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro (S-Edit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the power consumption in Flash ADC is 41.78μw. The Threshold Inverter Quantization (TIQ) technique is proposed to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also observed that the ADC consumes 41.78μW of peak power and 6.45μW of average power at full speed while it operates on a power supply voltage of 0.6V. Compared with the earlier work, this project consumes less power and high speed with proposed TIQ technique gives an edge in SoC based VLSI design. Finally the Signal to Noise Distortion analysis is done to obtain more precise data conversion results. The SNDR was found 31.9dB for ultimate precise data conversion using 45nm CMOS process technology.

Keywords: System-on-chip based design, flash ADC, Threshold Inverter Quantization technique, Modern VLSI design, SNDR, CMOS process technology.

[1] D. Lee, J. Yoo, and K. Choi, "Design Method and Automation of Comparator Generation for Flash A/D Converter", in Proceedings of the International Symposium on Quality Electronic Design (ISQED), pages 138-142, 2002.
[2] K. Uyttenhove and M. Steyaert, "A 1.8V, 6-bit, 1.3 GHz CMOS Flash ADC in 0.25μm CMOS", in Proceedings of the European Solid-State Circuits Conference, pages 455-458, 2002.
[3] C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, "A 6-bit 1.2GS/s Low-Power Flash ADC in 0.13μm Digital CMOS", IEEE Journal of Solid State Circuits, Vol. 40, no.7, pages 1499-1505, July 2005.
[4] C. Donovan and M. P. Flynn, "A Digital 6-bit ADC in 0.25μm CMOS", IEEE Journal of Solid State Circuits, vol. 37, no. 3, pages 432-437, March 2002.
[5] P.C.S. Scholtens, and M. Vertregt, "A 6b 1.6 Gsample/s Flash ADC in 0.18μm CMOS Using Averaging Termination", IEEE Journal of Solid State Circuits, vol. 37, no. 12, pages 1599-1609, December 2002.
[6] I. Mehr and D. Dalton, "A 500MSample/s, 6-bit Nyquist Rate ADC for Disk-Drive Read-Channel Applications", IEEE Journal of Solid State Circuits, vol. 34, no. 7, pages 912-920, July 1999.
[7] B.S. Song, P.L. Rakers, and S.F. Gillig, "A 1-V 6-bit 50MSamples/s Current-Interpolating CMOS ADC", IEEE Journal of Solid State Circuits, vol. 35, no. 4, pages 647-651, April 2000.
[8] K. Uyttenhove, A. Marques, and M. Steyaert, "A 6-bit 1GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction", in Proceedings of the Custom Integrated Circuits Conference, pages 249-252, 2000.
[9] V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, "A Distortion Compensating Flash Analog-to-Digital Converter", IEEE Journal of Solid State Circuits, vol. 41, no. 9, pages 1959-1969, September 2006.
[10] H.C. Tseng , C. Lin, H. Ou, and B. Liu, "A Low-Power Rail-to-Rail 6-bit Flash ADC based on a Novel Complementary Average-Value Approach", in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pages 252-256, 2004.

Paper Type : Research Paper
Title : Design of C-Band Microstrip Patch Antenna for Radar Applications Using IE3D
Country : India
Authors : V.Harsha Ram Keerthi, Dr.Habibullah Khan, Dr.P.Srinivasulu
: 10.9790/2834-0534958      logo

Abstract: In the recent years the development in communication systems requires the development of low cost, minimal weight and low profile antennas that are capable of maintaining high performance over a wide spectrum of frequencies. This technological trend has focused much effort into the design of a microstrip patch antenna. The objective of this paper is to design an microstrip line fed rectangular microstrip patch antenna which operates in C-band at 5GHz. Therefore, method of moments based IE3D software is used to design a Microstrip Patch Antenna with enhanced gain and bandwidth. IE3D is an integrated full-wave electromagnetic simulation and optimization package for the analysis and design of 3D and planar microwave circuits, MMIC, RFIC, RFID, antennas, digital circuits and high speed Printed Circuit Board (PCB). The IE3D has become the most versatile, easy to use, efficient and accurate electromagnetic simulation tool. The length of the antenna is nearly half wavelength in the dielectric it is a very critical parameter, which governs the resonant frequency of the antenna. In view of design, selection of the patch width and length are the major parameters along with the feed line dimensions. Desired patch antenna design was simulated by IE3D simulator program. The entire project is being carried out at National Atmospheric Research Laboratory (NARL), ISRO.

Key words: C-Band, IE3D, Micro strip Patch, RADAR, Wind profiler

[1] Srinivasulu. P, Manas R Padhy, Yasodha. P and NarayanaRao. T, 2010 "Development of UHF wind profiling radar for lower atmospheric research applications". Conference paper at NARL.

[2] Srinivasulu. P, Yasodha. P, Rajendra Prasad. Tand Narayana Reddy. S 2010 "Development of 1280 MHz Active Array RADAR at NARL". Conference Paper at NARL DRAWS-2010.

[3] C.T.P.Song, P.S.Hall and H.G.Shiraz, "Multiband Multiple Ring Monopole Antennas" IEEE Trans. on Antennas and propagation, vol. 51,No.4 pp. 722–729, April. 2003.

[4]. Karaboga, D., K. Guney, S. Sagiroglu, and M. Erler, \Neural computation of resonant frequency of electrically thin and thick rectangular microstrip antennas," IEEE Proceedings | Microwaves, Antennas and Propagation, Vol. 146, No. 2, 155{159, Apr. 1999.

[5]. Mishra, R. K. and A. Patnaik, \Neural network-based CAD model for the design of square-patch antennas," IEEE Trans. on Antennas Propagat., Vol. 46, No. 12, 1890{1891, Dec. 1998.

[6]. Patnaik, A., R. K. Mishra, G. K. Patra, and S. K. Dash, \An arti¯cial neural network model for e®ective dielectric constant of microstrip line," IEEE Trans. on Antennas Propagat., Vol. 45, No. 11, 1697, Nov. 1997.

[7] R. G. Voughan. 1988. Two-port higher mode circular microstrip antennas. IEEE, Trans. Antennas Propagat.36(3): 309-321.

[8] D.D.Sandu, O.Avadanei, A.Ioachima, G.Banciua, P.Gasner. Microstrip Patch Antenna with dielectric substrate. Journal Optoelectronics and Advanced Materials Vol. 5, No. 5, 2003.

Paper Type : Research Paper
Title : New chaotic binary sequences with good correlation property using logistic maps
Country : Algeria
Authors : Chikhaoui Fatima, Djebbari Ali
: 10.9790/2834-0535964      logo

Abstract: In this paper, schemes for generating binary sequences from logistic maps are proposed. Using new methods, several binary sequences with the same length can be generated directly by assuming different initial conditions to logistic maps. A comparison between conventional sequences (maximum length sequences, Gold sequences) and proposed sequences has been established, and demonstrate that our sequences are comparable and even superior to conventional sequences in several keys aspects, and they can be used as spreading sequences.

Keywords- Conventional sequences, correlation function, Direct Sequence Code Division Multiple Access (DSCDMA), logistic maps.

[1] G. Heidari-Bateni and C.D. McGillem, Chaotic Sequences for Spread Spectrum: An Alternative to PN-sequences, Proc. IEEE International Conference on Selected Topics in Wireless Communications, Vancouver, B.C, Canada, 1992, 437-440.

[2] G. Heidari-Bateni and C.D. McGillem, A Chaotic Direct-Sequence Spread Spectrum Communication System, IEEE Trans. On Communications. 42(2/3/4), 1994, 1524-1527.

[3] H. Saigui, Z. Yong, H. Jiandong and B. Liu, A synchronous CDMA system using discrete coupled-chaotic sequence, Proc. IEEE South-eastcon'96, 1996, 484-487.

[4] Xingang Wang, Meng Zhan, Xiaofeng Gong, Choy Heng Lai and Ying-Cheng Lai, Spread spectrum communication using binary spatiotemporal chaotic codes, Phys. Lett. A, 2005, 334, 30-36.

[5] Mahalinga V. Mandi, R. Murali and K.N. Haribhat, Chaotic functions for generating binary sequences and their suitability in multiple access, Proc. IEEE International Conference on Communication Technology, 2006, 1-4.

[6] Tien-Yien. Li and James.A. Yorke, Period three implies chaos, JSTOR, 82(10), 1975, 985–992.

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Paper Type : Research Paper
Title : Design of Low Noise Amplifier for Radio over Fiber at 5.2 GHz
Country : Malaysia
Authors : A. Salleh, M. Z. A Abd Aziz , N. R. Mohamad, M. A. Othman1, Z. Zakaria, M. H. Misran
: 10.9790/2834-0536569      logo

Abstract: This paper presents the design and simulation of low noise amplifier (LNA) used in an active radio access point (RAP) for Radio over Fiber (RoF) technology at 5.2 GHz. RoF is integration of optical fiber for radio signal transmission within network infrastructures that is considered to be cost effective, practical and relative system configuration for long haul transport of millimeter frequency band wireless signal. The LNA designed function is to amplify extremely low signals without adding noise, thus preserving the required Signal Noise Ratio (SNR) of system at extremely low power signal. The implementation of design is based on Agilent ATF-5143 transistor and Microwave Office software is used to perform the simulation in S-parameters. The design and simulation process including selecting the transistor based on RoF requirements, stability of transistor, matching network, biasing and optimization. The design has shown an acceptable behavior with gain of 16.046 dB and noise figure of 0.9368 dB using conjugate matching method. Keywords - LNA, RoF, RAP, Conjugate Matching Method, S-parameters

[1] P. P Smyth, "Optical Radio – A review of a Radical New Technology For Wireless Access Infrastructure," In: Peter Smyth. Mobile
and Wireless Communication: Key Technologies and Future Applications. London. : The Institution of Electrical Engineers, 2004.
[2] Hyo-Soon Kang, Myung-Jae Lee and Woo-Young Choi, "Multi Standard Radio over Fiber Systems using CMOS-Compatible Si
Avalanche Photodetector," Asia Pacific Microwave Photonics Conference, pp. 302–35, 2008.
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Boston, 2002.
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Paper Type : Research Paper
Title : FPGA Based System Login Security Lock Design Using Finite State Machine
Country : India
Authors : Kavita Saroch, Abhilasha Sharma
: 10.9790/2834-0537075      logo

Abstract: Field Programmable Gate Array (FPGA) delivers breakout performance capacity and system integration while optimizing to develop FPGA devices based on CAD tools in the Hardware Description Language (HDL), which illustrate the logic, function and behaviors of system hardware. VHDL (very high speed integrated circuit HDL) is one of the important hardware description language which is used in this research paper to design SYSTEM LOGIN SECURITY LOCK. This research paper introduces the security technology for machines or objects. In this we design an automatic Security System Login Lock using FSM based on FPGA. This can be done with the help of XILINX software. In this the lock can only opened when the desired code (password) is entered or the given sequence is detected by the system.


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[6] sascha kenrad,betty h.c. cheng,laura a.campbell, and ranold Wassermann, USING SECURITY PATTERNS TO MODEL AND ANALYZE SECURITY REQUIREMENTS, 2nd international workshop on requirements engineering for high assurance systems(rhas'03), september9, 2003.monterery bay, California, conjection with the 11th IEEE international requirements engineering conference.
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[10] R. Ramachandran, J. Thomas Joseph Prakash, FPGA Based SOC for Railway Level crossing Management System, International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-3, July 2012.

Paper Type : Research Paper
Title : Cascaded PID Controller Design for Heating Furnace Temperature Control
Country : India
Authors : Y V Pavan Kumar, Arvapalli Rajesh, Sadhu Yugandhar, Viswaraju Srikanth
: 10.9790/2834-0537683      logo

Abstract: The paper evaluates the performance of cascaded PID controller designs for the temperature control of an industrial heating furnace. From the control theory literature it is clear that ideal PID controller is an obsolete for the control of non-linear processes like temperature. PID controller in cascaded architecture is the best choice compared to conventional single loop control system for controlling these nonlinear processes. However, it is constrained in choosing the better PID gains. Hence, this paper is such an approach to set the better values of PID gains in cascaded form by evaluating the performance with conventional tuning formulas. Performance analysis of various algorithms was carried out by finding the system's dynamic performance characteristics in each case. The entire system is modeled by using MATLAB/Simulink, The simulation results indicate that the proposed cascaded PID design could results to rapidity in response with robust dynamic performance.

Keywords - Cascaded Control System, Dynamic performance analysis, PID (Proportional plus Integral plus Derivative) controller, Temperature process control, Matlab/Simulink, Tuning concepts.

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