Paper Type |
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Research Paper |
Title |
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Highly Programmable Test Pattern Generation with Optimized DFT Architecture for VLSI Testing |
Country |
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India |
Authors |
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C. Narmadha || G. Mohanraj |
Abstract: Many attempts have been carried out to overcome the bottleneck of test data bandwidth between the tester and the chip in the concept of combining BIST and test data compression. In this paper we present a new test data-compression scheme that is a hybrid approach between external testing and Built-In Self-Test (BIST). The proposed approach is based on Low-Power (LP) programmable generator capable of producing.......
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