iosr-JECE   Volume-1 ~ Issue-1

Abstract : The soft-computing techniques provide us with tools that can be used to calculate the various parameters that cannot be measured easily. In this paper computational study of DNA base Thymine has been carried out using two probe set up. The metal-molecule-metal assembly was realized by inserting Thymine molecule between two gold terminals and analyzed for current-voltage characteristics. The current-voltage characteristics are obtained using Density Functional theory within Non-equilibrium Green's function formalism (NEGF-DFT). Negative differential resistance is exhibited in the characteristics of Thymine. In two probe set-up without using gate, oscillating behavior of current through thymine is observed rendering its use to drive electronic circuits. It is also observed that the current-voltage characteristics of Thymine can be modulated by gating the two probe setup. The analysis shows that Thymine is suitable for use in two and three terminal Nanoelectronic devices.
Keywords: computation, DNA base Thymine, negative differential resistance, resonant tunneling.

[1] Deep Kamal Kaur Randhawa, M.L.Singh, Inderpreet Kaur, Lalit M. Bharadwaj, Single Electron Effects in DNA bases, IJAET/ Volume II/ Issue II/ 197-201/ April-June'2011
[2] K Stokbro, First-principles modeling of electron transport, Journal of Physics: Condensed Matter 20 064216 (7pp) (2008)
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[6] Deep Kamal Kaur Randhawa, Lalit M Bharadwaj, Inderpreet Kaur and M.L.Singh, DNA Bases as Molecular Electronic Devices, International Journal of Computer Applications 19(2):39-43, April 2011.
[7] Haiying He, Ravinda pandey, Asymmetric Currents in a Donor−Bridge−Acceptor Single Molecule: Revisit of the Aviram−Ratner Diode, J. Phys. Chem. C, 113 (4), pp 1575–1579( 2009)
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[9] Elizabeth Tran, Marco Duati, Violetta Ferri, Klaus Müllen, Michael Zharnikov, George M. Whitesides, and Maria A. Rampi, Experimental Approaches for Controlling Current Flowing through Metal–Molecules–Metal Junctions, Adv. Mater. ,18, 1323–1328(2006)
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ABTRACTS : In this paper VHDL implementation of 8-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and subtraction using 8-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1's and 2's complement operations and compare. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 8-bit fast adder with 2's complement circuit to perform subtraction and logic gates to perform logical operation. The maximum propagation delay is 13.588ns and power dissipation is 38mW. The ALU was designed for controller used in network interface card.
KEYWORDS : ALU, Fast adder, Network interface card, VHDL implementation.

[1] Toshio Fujisawa, et al, "A Single-Chip 802.11a MAC/PHY With a 32-b RISC Processor", in IEEE Journal Of Solid-State Circuits, Vol. 38, No. 11, November 2003.
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[8] J. Bhaskar, " VHDL Synthesis Primer", Pearson Education, 1st Edition, 2002.

ABSTRACT: Smart adaptive antenna technology is considered to be the last technology frontier that has the potential of leading to large increases in systems performance. Time domain techniques have been extensively exploited. Space domain techniques, on the other hand, have not been exploited to the same extent. When applied to wireless, the benefits of smart adaptive array a antennas are as follows: (i) increased covered, which is important in the early stages of life cycle, (ii) increased capacity, which is important in the later stages of life cycle, (iii) improved link quality, (iv) reduced costs and increased return on investment, (v) lower handset power consumption, and (vi) assistance in user location by means of direction finding. This paper discusses an experimental neural network based smart antenna capable of performing direction finding and the necessary beam forming. The algorithm operates in two stages. The field of view of the antenna array is divided into spatial sectors ,then each network is trained in the first stage to detect signals emanating from sources in that sector. According to the outputs of the first stage, one or more networks of the second stage can be activated so as to estimate the exact location of the sources. No a priori knowledge is required about the number of sources, and the networks can be designed to arbitrary angular resolution. Some experimental results are shown and compared with other algorithms, such as, the Fourier Transform and the MUSIC algorithm AND ESPRIT variations is done in the proposed research work.
Keywords: DOA ,MUSIC,ESPRIT

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Abstract: circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on Wallace tree technique. Clocked architecture results in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. Higher order multipliers like 16x16, 32x32 may also be implemented using 4x4 bit multiplier and hence a modular design is presented by constructing an 8x8 multiplier using multiple 4x4 multipliers. Average power and TannerTool report for 8x8 Multiplier is as follows, Device and node counts: MOSFETs – 2572, MOSFET geometries - 2 Measurement result summary Average Power found to be 0.11108 microwatt

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ABSTRACT: With the development of micro electronics and information technology, there are more pixels in unit area of the imaging device. The high resolution images with more pixels can be obtained easily. But the high resolution images have huge data volume. It is difficult to transmit, to process, to store high resolution images. So compressing images is an important technology to reduce the requisite storage space and transmission channel bandwidth. In this paper multiwavelet coding has been proved to be a very effective technique for medical images giving significantly better results. The Discrete Multiwavelet Transform of the image is calculated with Geronimo- Hardin - Massopust (GHM) multiwavelet. The wavelet coefficients are encoded using SPIHT coder. This method yields better compression performance. The quality of the image is assessed by PSNR value, Compression Ratio and Coding times.
KEYWORDS: DiscreteMultiwaveletTransform(DMWT), Geronimo- Hardin - Massopust (GHM) multiwavelet, Good Multifilter Propertity (GMP), Set Partitioning In Hierarchical Trees (SPIHT), Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR), Coding times(Encoding and Decoding times).

[1] S. Esakkirajan, T. Veerakumar, V. Senthil Murugan, P. Navaneethan (Aug 2008), "Image Compression Using Multiwavelet and Multi-stage Vector Quantization", World Academy of Science, Engineering and Technology 48.
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[6] Ren Zhengyun Multimedia computer technology [M]Beijing: China water conservancy and hydropower press 2009.7
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ABSTRACT: According to the result of moving object detection research on video sequences, this paper proposes a new method to detect moving object based on background subtraction. First of all, we establish a reliable background updating model based on statistical and use a dynamic optimization threshold method to obtain a more complete moving object. And then,morphological filtering is introduced to eliminate the noise and solve the background disturbance problem. At last, contour projection analysis is combined with the shape analysis to remove the effect of shadow, the moving human body are accurately and reliably detected. The experiment results show that the proposed method runs quickly, accurately and fits for the real-time detection. The occlusion is one of the most common events in object tracking and object centroid of each object is used for detecting the occlusion and identifying each object separately. Video sequences have been captured in the laboratory and tested with the proposed algorithm. The algorithm works efficiently in the event of occlusion in the video sequences.
Keywords-background subtraction; background model; moving object detection , shadow removal and occlusion detection.

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ABSTRACT : In this paper, we propose an architecture for controlling Dynamic Reconfigurable systems. The processor instructions when compiled one by one produces very high delay overhead. If these instructions are converted into a combinational logic then the overhead can be reduced thereby making the system an efficient one. This paper presents a method for creating the control logic necessary for performing operations on instructions. The proposed design is simulated using Modelsim 10.0c.The area and power constraints are evaluated using Synopsys Design Compiler.
Keywords - Functional Unit, MIPS, Multistage Interconnection Network, Omega MIN, Reconfigurable system.

Proceedings paper
[1] Ricardo Ferreira,Cristoferson Bueno, Marcone Laure,Monica Pereira and Luigi Carro "A Dynamic Reconfigurable Super VLIW Architecture for a Fault Tolerant Nanoscale Design" 4TH HiPEAC Workshop on Reconfigurable Computing,pp.7-16,January 2010
[2] A. Beck, M. Rutzig, G. Gaydadjiev, L. Carro, "Transparent reconfigurable acceleration for heterogeneous embedded applications," in DATE ‟08: Proceedings of the conference on Design, automation and test in Europe, pp.1208–1213, March 2008 [3] Tse-yun Feng, "A Survey of Interconnection Networks," IEEE, pp.12-27, December 1981.
[3] Berticelli Lo, T. Beck, A.C.S. Rutzig, M.B. Carro, L, "A low-energy approach for context memory in reconfigurable systems" IEEE International Symposium on Parallel & Distributed Processing, Workshops and PhD Forum (IPDPSW), pp.1-8, April 2010.
[4] K. Tanigawa, T. Zuyama, T. Uchida, and T. Hironaka, "Exploring compact design on high throughput coarse grained reconfigurable architectures," in FPL ‟08: Proceedings of the International Workshop on Field-Programmable Logic, pp. 126–135, September 2008.
Conference paper
[5] G. Mehta, J. Stander, M. Baz, B. Hunsaker, and A. K. Jones, "Interconnect customization for a coarse-grained reconfigurable fabric," International Parallel and Distributed Processing Symposium (IPDPS), pp.1-8, March 2007.
Text book
[6] Antonio Carlos Schneider Beck Fl, Luigi Carro, Dynamic reconfigurable architectures and transparent optimization techniques, Springer Dordrecht Heidelberg London,2010.

ABSTRACT :This paper compares 4 different multipliers and the one with the least area and power is applied in 1D-DWT. The multipliers are implemented using booth algorithms as well as Wallace tree structures. The advantage of using Modified Booth algorithm is that the number of partial products is reduced by half. The Wallace tree structure is used for partial product reduction. 1D-DWT is implemented using modified Wallace tree structures alone as it has the least area and power. The 1D-DWT is mainly used for image compression.
Keywords - Modified Booth algorithm, Wallace trees, 1D-DWT.

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[2] Ron S. Waters and Earl E. Swartzlander, A Reduced Complexity Wallace Multiplier Reduction, IEEE TRANSACTIONS ON COMPUTERS, VOL. 59, NO. 8, AUGUST 2010
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[10] Soojin Kim and Kyeongsoon Cho, "Design of high-speed modified booth multipliers operating at GHz ranges", World Academy of Science, Engineering and Technology 61 2010