iosr-JECE   Volume-1 ~ Issue-4

Abstract : 4G is a brand name for the Fourth Generation of the cellular wireless standards. Over the years, Nigerian telecommunication firms have been in operation with predecessor generation standards (such as 2G and 3G). The design principle of each of these cellular wireless standards follow the same principle, where the information to be transmitted will pass from transmitter through a channel to the receiver at a frequency within the allowable band. For a long distance transmission to take place, information to be transmitted need to be modulated with high frequency also known as carrier frequency. This implies that for any licensed telecom firm in Nigeria, a carrier frequency slot from the regulatory body must be allotted. This research work aims to study the practice of telecommunications in Nigeria vis-à-vis the latest 4G technology around the world; identify the existing technologies in Nigeria; identify the limitations of Telecommunication Service Providers (TSPs) in Nigeria that may be responsible for delay (if any) in migration to 4G technology. The research methodology that was adopted in this research is the survey, interview, questionnaires and the use of statistical analysis tool (SPSS).
Keywords: Telecommunication, Communication, Fourth Generation (4G), Transmission

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ABTRACTS : Wide bandgap, high saturation velocity, and high thermal stability are some of the properties of GaN, which make it an excellent material for high-power, high-frequency, and high-temperature applications. As several application areas require the devices to operate at elevated power range, a proper modeling of the device using the property of band structure and transport parameters is very important.Progress on materials development includes the development of AlGaN and AlN barrier HEMTs with room temperature electron mobility nearly 2000 cm2/ V-s. Trap free GaN HEMT devices over12 W/mm power density and device operating at frequencies nearly to 300 GHz are presented. We present two-dimensional simulations of AlGaN/GaN high electron mobility transistors (HEMTs) at high frequencies are carried out with Silvaco ATLAS tool. The 2DEG dependence of the maximum current and cut-off frequency of submicron devices is further studied.
KEYWORDS : HEMT, 2DEG, ATLAS, Heterostructure, Nucleation Layer

[1] Arulkumaran S, Egawa T, Ishikawa H, Jimbo T. High-temperature effects of AlGaN/GaN high-electron-mobility transistors on sapphire and semiinsulating SiC substrates. Appl Phys Lett 2002;80(12):2186–8.
[2] Arulkumaran S, Liu Z, Ng G, Cheong W, Zeng R, Bu J, et al. Temperature dependent microwave performance of AlGaN/GaN high-electron-mobility transistors on high-resistivity silicon substrate. Thin Solid Films 2007;515(10):4517–21.
[3] Vurgaftman I, Meyer J, Ram-Mohan L. Band parameters for III–V compound semiconductors and their alloys. J Appl Phys 2001;89(11):5815–75.
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[5] Yoshida S, Misawa S, Gonda S. Properties of AlxGa1_xN films prepared by reactive molecular beam epitaxy. J Appl Phys 1982;53(10):6844–8.
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[7] Westmeyer A, Mahajan S, Bajaj K, Lin J, Jiang H, Koleske D, et al. Determination of energy-band offsets between GaN and AlN using excitonic luminescence transition in AlGaN alloys. J Appl Phys 2006;99(1):013705(4).
[8] Ambacher O, Foutz B, Smart J, Shealy J, Weimann N, Chu K, et al. Twodimensional electron gases induced by spontaneous and piezoelectric polarization in undoped and doped AlGaN/GaN heterostructures. J Appl Phys 2000;87:334–44.
[9] M.C.J.C.M. Krämer, R.C.P. Hoskens, B. Jacobs, J.J.M. Kwaspen, E.M. Suijker, A.P. de Hek, F. Karouta, and L.M.F. Kaufmann, "Dispersion free doped and undoped AlGaN/GaN HEMTs on sapphire and SiC substrates," Proc. Gallium Arsenide and other Compound Semiconductors Application Symposium 2004 (GAAS 2004), p75, 11 - 15 October 2004, Amsterdam, The Netherlands.
[10] Y. Ando, Y. Okamoto, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, and M. Kuzuhara, "12 W/mm recessed-gate AlGaN/GaN heterojunction field-plate FET," Proc. IEEE International Electron Devices Meeting. IEEE, p 563, 2003.

ABSTRACT: This work implements a software based SMS switching system using GLOBACOM and MTN as network carriers. JAVA programming language with focus on socket programming will be used for the software development. The application client, which is the portion that runs on the mobile phone, uses Java macro Edition, while the server section involved in the switching uses Java Servlet. When tested on the windows 7 operating system using oracle and the SUN mobile phone simulators, there was quick response and transmission of the SMS text from one end to the other. The application was similarly simulated on the UNIX based operating system such as Linux, and Solaris. There was high level of success on the simulation showing that the results are reliable. However the results could only handle up to 100 characters per SMS and a 64 bit encryption technique was used. Keywords: gateway; IP; Java; module; SMS

[1] Hillebrand, Trosby, Holley, Harris (2010) SMS the creation of Personal Global Text Messaging, Wiley
[2] Tomasi, Wayne (2004) Introduction to Data Communications and Networking, 1st ed. Upper Saddle River, NJ: Prentice Hall.
[3] Gil Held (2001) "Data over Wireless Networks". Wiley, NJ
[4] Gredle Rose (2005) GSM standards and services publication of IEEE, 2005
[5] Rheingold Victor (2002). Mobile Computing Handbook. Artech House Mobile Communications Library. Artech House..
[6] Sun Microsystems (2009), Java 2 Platform, Micro Edition (J2METM Platform).Available as http://java.sun.com/j2me/
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Abstract: Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. With the advancements in technology, research is still going on to design a multiplier that consumes less power or has high speed or occupies less area or a combination of these in a single multiplier. This makes the multipliers to be used for high speed or low power VLSI applications. The Braun's multiplier is one of the parallel array multiplier which is used for unsigned numbers multiplication. The dynamic power of the multiplier can be reduced by using the bypassing techniques. The delay can be reduced by replacing the ripple carry adder in the last stage by fast adders like Carry look ahead adder and Kogge stone adder. This paper presents a comparative study among different types of bypassing multipliers for 4*4, 8*8 and 16*16 bits and their architectural modifications using different FPGAs like Spartan – 3E, Virtex – 4, Virtex – 5 and Virtex – 6 Lower power using Xilinx 13.2 ISE tool from which we get the delay and the dynamic power and cell area reports are obtained using RTL Compiler from Cadence in 90 nm technology.
Keywords: Field Programmable Gate Array (FPGA), Bypassing Techniques, Digital Signal Processing, Multipliers, Carry Look Ahead adder, Kogge stone adder

[1] M. C. Wen, S. J. Wang and Y. M. Lin, "Low power parallel multiplier with column bypassing," IEEE International Symposium on Circuits and Systems, 2005.
[2] J. Ohban, V. G. Moshnyaga, K. Inoue, "Multiplier energy reduction through Bypassing of partial products", IEEE Asia-Pacific Conference on Circuits and Systems, pp.13-17, 2002.
[3] G.N.Sung, Y.J.Ciou, C.C.Wang, "A power aware 2-dimensional bypassing multiplier using cell – based design flow", IEEE International Symposium on Circuits and Systems, 2008.
[4] J. T. Yan, Z. W. Chen, "Low-power multiplier design with row and column bypassing," IEEE International SOC Conference, pp. 227-230,2009.
[5] Muhammad H. Rais, "Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices", Am. J. Engg. & Applied Sci., 2010.
[6] R. Anitha, V. Bagyaveereswaran, "Braun's Multiplier Implementation using FPGA with Bypassing Techniques", International Journal of VLSI Design and Communication Systems (VLSICS) Vol. 2, No. 3, September, 2011.
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[8] David H. K. Hoe, Chris Martinez and Sri Jyosthna Vundavelli, "Design and Characterization of Parallel Prefix adders using FPGAs", IEEE 2011.
[9] Neil H.E.Weste, David Harris, Ayan Banerjee, "CMOS VLSI Design, A circuits and system perspective", Pearson education, 2009.
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ABSTRACT: Programmable Logic Controller (PLC) is a device that allows an Electro-Mechanical engineer to automate his mechanical process in an efficient manner. PLC is a typical Microprocessor or Micro-Controller based system with its dedicated operating system to interpret the control specification, scan inputs and accordingly activate the final control elements. As the number of rungs of the ladder diagram increases or the control specification logic becomes more complex, the time taken by the PLC also increases. This results in failure to respond during safety critical situation. This happens because: in conventional PLC's, the control specifications are first converted into intermediate instruction list and then this intermediate list of instructions is converted into op-codes that are compatible with processing core inside PLC. This increases the total code length for the PLC processor. Increased code length means increased execution time. Work in this paper proposes to design IEC61131-3 compliant instruction list processor using FPGA for better response time. Such application specific processor design is expected to provide significant improvements in overall system performance and quality of the control and automation systems. Tests to the design, used platform, resources consumed and relevant conclusions of proposed IL processor are included here.
KEYWORDS: PLC PROCESSOR; INSTRUCTION SET; ARCHITECTURE; IEC61131-3

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[2] Shuting-zeng , Zhijia-yang, "High performance architecture design of PLC dedicated processor" Industrial informatics laboratory Shenyang institute of automation, Graduate School of the Chinese Academy of Sciences Shenyang, China 978-1-4244-6542-2/$26.00 © 2010 IEEE
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ABSTRACT: A CMOS LNA design and Gilbert double balanced mixer design for indoor wireless application are presented in this paper. The LNA is designed with current reused technology for lowering the dc power consumption, and the current-bleeding approach is adopted in mixer design for boosting its conversion gain, respectively. The Narrow band LNA achieves the gain of 20dB with noise figure of 1.5dB at 787MHz. The power consumption of LNA is 21.793μW. The proposed Gilbert double balanced mixer achieves the conversion gain of 13.365dB with Noise Figure of 2.12db and IIP3 as -2.8634dB for intermediate frequency of 100 KHz to 100MHz.

1. A 24GHz low-power CMOS receiver design, Chen-Yuan�Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng and Wu-Shiung Feng Department of Electronic Engineering Chang Gung University
2. Kwei-Shan, Tao-Yuan, Taiwan
3. IEEE journal 2008.
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5. Behzad Razavi, "A 24-GHz CMOS Front-End", IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp.368-373, Feb 2004.
6. Hsieh-Hung Hsieh, and Liang-Hung Lu, "Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures", IEEE Trans. Microw. Theory Tech., vol. 55, no. 7, pp. 1445-1458, July 2007.
7. Ghazinour, A., Wennekers, P., Schmidt, J., Yin Yi, Reuter, R., and Teplik, J, "A fully-monolithic SiGe-BiCMOS transceiver chip for 24 GHz applications", IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp.181-184, 2003.
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9. International Journal of Control and Automation Vol. 3, No. 2, June, 2010 Performance Analysis of CMOS Single Ended Low Power Low Noise Amplifier (1)Mayank Chakraverty, (2)Sandeep Mandava, (3)Gargi Mishra (1),(2) M.Tech. Nanoelectronics , (3) M.Tech.Sensor System Technology School of Electronics Engineering, VIT University, Vellore, India. 1)mayank2010.
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12. A 60-GHz CMOS Receiver Front-End Behzad Razavi, Fellow, IEEE.Vol. 30, No. 10 Journal of Semiconductors October 2009.
13. A novel noise optimization technique for inductively degenerated CMOS LNA Geng Zhiqing, Wang Haiyong, and Wu Nanjian. (State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors).
14. 11. Heng Zhang, Student Member, IEEE, and Edgar Sánchez-Sinencio, Life Fellow, IEEE Transactions on Circuits and Systems—I: Regular papers, Vol. 58, No. 1, January 2011.
15. Wei-Hsiang Hung, Kuan-Ting Lin, Jian-Yu Hsieh, and Shey-Shi Lu Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwanr96943052,d96943005,d99943020,sslu@ntu.edu.tw.

ABSTRACT : Operating an Integrated circuit at the prescribed Voltage scaling (constant field scaling) is preferable for reliable circuit operation under temperature fluctuations. In this work we proposed to design 1 –bit full adder by "changing the threshold voltage and W/L ratio" under temperature variation insensitive conditions. We measured power consumption, leakage current, noise margin, layout area, etc parameters. The results are compared with the previous work and shown that Power is saved 92%, 1% of leakage current and 15% of noise margin. We have performed simulations using 90 Nanometer (nm) Micro wind 3 CMOS layout CAD Tool for design. Key words: voltage scaling, threshold voltage, W/L ratio, Temperature variation, noise margin, leakage current (Ion+Ioff).

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