Abstract: Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold
voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We
analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for
ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design
requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better readstability
as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to
propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and
less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were
done using DSCH and Microwind.
Index Terms: read stability, write ability, Schmitt trigger.
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