iosr-JECE   Volume-6 ~ Issue-5

Abstract: In any computing environment, it is necessary for the processor to have fast accessible RAM that allows temporary storage of data. DDR3- SODIMM module is a key component in the memory interface and is becoming increasingly important in enabling higher speeds. Considering higher bandwidths and speeds more than 1GHz, DDR3 is enabling poses more and more high speed signaling and design challenges. Characterized SODIMM module need to be designed to understand and analyze the impact of SODIMM parameters at higher speeds and thereby define more robust memory interface. This will include simulation, board design, validation and results correlation and involves high speed simulation and validation methodologies.

Keywords – Validation, Correlation, DDR3, Characterized SODIMM, Signal Integrity

[[1] Li, P. ; Martinez, J. ; Tang, J. ; Priore, S. ; Hubbard, K. ;Jie Xue ; Poh, E. ; Ong MeiLin ; Chok KengYin ; Hallmark, C. ;Mendez, D.
Development and evaluation of a high performance fine pitch SODIMM socket package, 1161 - 1166 Vol.1, IEEE,2004.
[2] PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 Un buffered SO-DIMM Reference Design Specification, Revision 0.71 draft.
[3] JEDEC STANDARD DDR3 SDRAM Specification (Revision of JESD79-3A, September 2007).
[4] PCB design tutorial and Orcad capture user guide.
[5] Infiniium DSO80000B Series Oscilloscopes and InfiniiMax Series Probes 2 GHz to 13 GHz Real -time Oscilloscope Measurement
Systems data sheet.
[6] Infiniium Series Oscilloscope Probes, Accessories, and Options Selection Guide Data Sheet.
[7] 1168A and 1169A InfiniiMax Differential and Single-ended Probes user guide.
[8] HSPICE® Simulation and Analysis User Guide Version Z-2007.03, March 2007.
[9] HSPICE Signal Integrity Guide U-2003.03-PA, March 2003.

Abstract: This paper presents the design exploration of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation.

Keywords-Booth encoder; low power; spurious power suppression technique(SPST); SPST-Adder.

[1] K. H. Chen, K. C. Chao, J. I. Guo, J. S. Wang, and Y. S. Chu, "Design exploration of a spurious power suppression technique (SPST) and its applications," in Proc. IEEE Asian Solid-State Circuits Conf., Hsinchu, Taiwan, Nov. 2005, pp. 341–344.
[2] A. Bellaouar and M. I. Elmasry, "Low-Power Digital VLSI Design" Circuits and Systems. Norwell, MA: Kluwer, 1995.
[3] A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, no. 4, pp. 498–523, Apr. 1995.
[4] K. K. Parhi, "Approaches to low-power implementations of DSP systems," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 10, pp. 1214–1224, Oct. 2001.

Abstract: In any computing environment, it is necessary for the processor to have fast accessible RAM that allows temporary storage of data. DDR3- SODIMM module is a key component in the memory interface and is becoming increasingly important in enabling higher speeds. Considering higher bandwidths and speeds more than 1GHz, DDR3 is enabling poses more and more high speed signaling and design challenges. Characterized SODIMM module need to be designed to understand and analyze the impact of SODIMM parameters at higher speeds and thereby define more robust memory interface. This will include simulation, board design, validation and results correlation and involves high speed simulation and validation methodologies.

Keywords – Validation, Correlation, DDR3, Characterized SODIMM, Signal Integrity

[1] E. Cands, "Compressive sampling," in Proc. Int. Congr. Mathematics,Madrid, Spain, 2006, pp. 1433–1452.

[2] X.Wu,K.U. Barthel, and W. Zhang, "Piecewise 2-D autoregression forpredictive image coding," in Proc. IEEE Int. Conf. Image Processing,Chicago, IL, Oct. 1998, vol. 3, pp. 901–904.

[3] X. Li and M. T. Orchard, "Edge-direted prediction for lossless compressionof natural images," IEEE Trans. Image Process., vol. 10, no.6, pp. 813–817, Jun. 2001.

[4] W. Lin and D. Li, "Adaptive downsampling to improve image compressionat low bit rates," IEEE Trans. Image Process., vol. 15, no. 9,pp. 2513–2521, Sep. 2006.

[5] L. Gan, C. Tu, J. Liang, T. D. Tran, and K.-K. Ma, "Undersampledboundary pre-/post-filters for low bit-rate dct-based coders," IEEETrans. Image Process., vol. 16, no. 2, pp. 428–441, Feb. 2007.

[6] X. Zhang, X. Wu, and F. Wu, "Image coding on quincunx lattice withadaptive lifting and interpolation," in Proc. IEEE Data CompressionConf., Mar. 2007, pp. 193–202.

[7] D. Santa-Cruz, R. Grosbois, and T. Ebrahimi, "Jpeg 2000 performanceevaluation and assessment," Signal Process.: Image Commun., vol. 1,no. 17, pp. 113–130, 2002.

[8] A. M. Bruckstein, M. Elad, and R. Kimmel, "Down-scaling for bettertransform compression," IEEE Trans. Image Process., vol. 12, no. 9,pp. 1132–1144, Sep. 2003.

[9] Y. Tsaig, M. Elad, and P. Milanfar, "Variable projection for near-optimalfiltering in low bit-rate block coders," IEEE Trans. Circuits Syst.Video Technol., vol. 15, no. 1, pp. 154–160, Jan. 2005.

Abstract: In this Paper, Analysis of channel codes for improving the data rate and reliability of communication over fading channels using multiple transmit antennas has been considered. The codes, namely 'Space Time Codes' render full diversity and amend coding gain. Performance criteria for designing such codes, under this assumption that the fading is slow and nonselective frequency, is also analysed. Under this research, Study of Frame Error Rate(FER) and outage capacity is compared for different no. Of transmit and receive antennas as well as for different modulation techniques. According to theoretical results FER decreases with increasing SNR and No. Of receiving antennas. Numerical and practical result shows that FER decreases with increasing SNR and no. Of receiving antennas. Keywords: Space time Block Codes ,Space time trellis Codes,Frame Error Rate(FER),Outage capacity,Pairwise Error Probability

[1] Ayman F. Naguib and R.Calderbank, "Space-Time Coding and Signal Processing for high data rate Wireless Communications ", Proc of Wireless Communication and Mobile Computing, Pg:13-34, 2001.

[2] Z.Liu, AG.B. Giannakis, B. Muquet, and S. Zhou, "Space-time coding for broadband wireless communications," Wireless Syst. Mobile Comput., vol.1, no. 1,pp.33-53,Jan.-Mar. 2001. [3] A.F. Naguib, N. Seshadri, and R. Calderbank,"Increasing date rate over wireless channels," IEEE Signal Processing Mug., vol. 17,pp. 76-92, May-2000.

[4] V. Tarokh, H. Jafarkhani, and A.R. Calderbank,"Space –time block codes from orthogonal designs," IEEE Trans. Inform. Theory,vol. 45, pp. 1456-14567,July 1999.

[5] S.M. Alamouti, "Simple transmit diversity technique for wireless communications ", IEEE Journal on Select Areas in Communications, vol. 16, pg. 1451-1458, 1998.

[6] Simon Haykin, "Communication Systems" - 3rd edition, John Wiley & Sons, Inc.1994.

[7] Herbert Taub, Donald L. Schilling, "Principles of Communication Systems " - 2nd edition , Tata McGraw Hill PublishingCompany, 1991.

[8] Sanjeev Kr., " Performance analysis of STTC using PSK modulation ", IJEECE, vol.2(7), pag 484-491, 2012.

Abstract:In recent years, multi-level cell (MLC) flash memories have been developed as an effective solution for increasing the storage density and reducing the cost of flash memories. MLC flash memories are especially for NAND flash memories . Error control coding (ECC) is essential for correcting errors in Flash memories.In order to correct multiple random errors and burst errors, an efficient decoding algorithms are required.In this work (255, 231) Product Reed-Solomon (RS) code technique for non-volatile NAND flash memory system sare used. In this proposed code that is Product Reed Solomon can correct both multiple random errors and burst errors. The Product Reed Solomon code consists of two shortened Reed-Solomon codes and a conventional Reed- Solomon code. It can correct up to certain symbol errors. A simulation result shows that the code has improved the coding gain and low power consumption. Keywords: Mlc Nand Flash Memory, Reed-Solomon Code

[1] S. P. Kang, C. G. Kim, S. W. Rhee, and Y. Jee, "ASIC Implementation of Reed-Solomon Error Correction Circuits for Low Area Overhead on Memory System," International Cnference on Electronics, Information, and Communication (ICEIC 2008), pp. 339-342, June. 2008.

[2] B. Chen and X. Zhang, "Error Correction for Multi-Level NAND Flash Memory Using Reed-Solomon Codes," IEEE Workshop on Singal Processing Systems (SiPS), pp. 94-99, Oct. 2008.

[3] R. Micheloni, R. Ravasio, A. Marelli, et. al, "A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput," IEEE Inter. Solid-State Circuits Conf., Feb. 2006.

[4] F. Sun, K. Rose and T. Zhang, "On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity," IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2006

[5] W. Liu, J. Rho and W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND Flash memories," IEEE Workshop on Signal Processing Systems (SIPS), pp. 248- 253, 2006.

[6] R. Micheloni, R. Ravasio, and A. Marelli, et. al, "A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read 284Throughput," IEEE Inter. Solid-State Circuits Conf, pp. 497-506 Feb. 2006.

[7] F. Sun, K. Rose, and T. Zhang, "On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity," IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2006.

[8] W. Liu, J. Rho, and W. Sung, "Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories," IEEE Workshop on Signal Processing Systems (SiPS), pp. 248-253, 2006.

[9] K. Viswajith Seth, K.N. Srinivasan and S. Kamakoti, "Ultra folded high-speed architectures for Reed Solomon decoders," VLSI Design‟06, pp.1063-9667, Jan. 2006.

[10] M. Mehnert, D. F. von Droste, and D. Schiel, "VHDL Implementation of a (255, 191) Reed Solomon Coder for DVB-H," IEEE 10th International Symposium on Consumer Electronics (ISCE), pp. 1-5, 2006.

Abstract: Adders are known to have the frequently used in VLSI designs. In digital design we have half adder and full adder, main adders by using these adders we can implement ripple carry adders. RCA use to perform any number of addition. In this RCA is serial adder and it has commutation delay problem. If increase the ha&fa simultaneously delay also increase. That's why we go for parallel adders(parallel prefix adders). IN the parallel prefix adder are ks adder(kogge-stone),sks adder(sparse kogge-stone),spaning tree and brentkung adder. These adders are designd and implemented on FPGA sparton3E kit. Simulated and synthesis by model sim6.4b, Xilinx ise10.1.

[1] N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th edition, Pearson–Addison-Wesley, 2011.
[2] R. P. Brent and H. T. Kung, "A regular layout for parallel adders," IEEE Trans. Comput., vol. C-31, pp. 260-264, 1982.
[3] D. Harris, "A Taxonomy of Parallel Prefix Networks," in Proc. 37th Asilomar Conf. Signals Systems and Computers, pp. 2213–7, 2003.
[4] P. M. Kogge and H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans. on Computers, Vol. C-22, No 8, August 1973.
[5] P. Ndai, S. Lu, D. Somesekhar, and K. Roy, "Fine-Grained Redundancy in Adders," Int. Symp. on Quality Electronic Design, pp. 317-321, March 2007.
[6] T. Lynch and E. E. Swartzlander, "A Spanning Tree Carry Lookahead Adder," IEEE Trans. on Computers, vol. 41, no. 8, pp. 931-939, Aug. 1992.
[7] D. Gizopoulos, M. Psarakis, A. Paschalis, and Y. Zorian, "Easily Testable Cellular Carry Lookahead Adders," Journal of Electronic Testing: Theory and Applications 19, 285-298, 2003.
[8] S. Xing and W. W. H. Yu, "FPGA Adders: Performance Evaluation and Optimal Design," IEEE Design & Test of Computers, vol. 15, no. 1, pp. 24-29, Jan. 1998.
[9] M. Bečvář and P. Štukjunger, "Fixed-Point Arithmetic in FPGA," Acta Polytechnica, vol. 45, no. 2, pp. 67-72, 2005.
[10] K. Vitoroulis and A. J. Al-Khalili, "Performance of Parallel Prefix Adders Implemented with FPGA technology," IEEE Northeast Workshop on Circuits and Systems, pp. 498-501, Aug. 2007.

Abstract: This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements.

Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.

[1] J. E. Volder, "The CORDIC trigonometric computing technique," IRE Trans. Electron. Comput., vol. EC-8, pp. 330–334, Sep. 1959. [2] K. Maharatna, A. S. Dhar, and S. Banerjee, "A VLSI array architecture for realization of DFT, DHT, DCT and DST," Signal Process., vol. 81, pp. 1813–1822, 2001.

[3] P. K. Meher, J.Walls, T.-B. Juang, K. Sridharan, and K. Maharatna, "50 years of CORDIC: Algorithms, architectures and applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 1893–1907, Sep. 2009.

[4] C. S. Wu and A. Y. Wu, "Modified vector rotational CORDIC (MVRCORDIC) algorithm and architecture," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 48, no. 6, pp. 548–561, Jun. 2001.

[5] C.-S.Wu, A.-Y.Wu, and C.-H. Lin, "A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no. 9, pp. 589 601, Sep.2003.

[6] Y. H. Hu and S. Naganathan, "An angle recoding method for CORDIC algorithm implementation," IEEE Trans. Compute., vol. 42, no. 1, pp. 99–102, Jan. 1993.

[7] M. G. B. Sumanasena, "A scale factor correction scheme for the CORDIC algorithm," IEEE Trans. Compute., vol. 57, no. 8, pp. 1148–1152, Aug. 2008.

[8] J. Villalba, T. Lang, and E. L. Zapata, "Parallel compensation of scale factor for the CORDIC algorithm," J. VLSI Signal Process. Syst., vol. 19, no. 3, pp. 227–241, Aug. 1998.

[9] L. Vachhani, K. Sridharan, and P. K. Meher, "Efficient CORDIC algorithms and architectures for low area and high throughput implementation," IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 61–65,Jan. 2009.

[10] K. Maharatna, S. Banerjee, E. Grass, M. Krstic, and A. Troya, "Modifiedvirtually scaling-free adaptive CORDIC rotator algorithm and architecture,"IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 11,pp. 1463–1474, Nov. 2005