iosr-JMCE   National Conference on Research Initiative in Science and Technology – 2K16

Paper Type	:	Research Paper
Title	:	Development and Study on Various Properties of Titanium Oxide -Tri Calcium Phosphate Composites through Powder Metallurgy Technique
Country	:	India
Authors	:	Sourav Debnath || Sourav Basu || Akshay Kumar Pramanick

Abstract: In this study, we made an attempt to develop titanium oxide-tricalcium phosphate (TiO2-TCP) composites due to its excellent biocompatible properties and performance. Pure β-tricalcium phosphate wasprepared via a wet precipitation process and studied its physical and mechanical properties. The synthesized β-tricalcium phosphate powder was analyzed for their phases and functional groups using X-ray diffraction technique (XRD) and Fourier Transform Infrared Spectroscopy (FTIR) respectively. Different quantities (3wt. %, 5 wt.%, and 10 wt. %) of Titanium oxide (TiO2) were incorporated into β-tricalcium phosphate to fabricate the composites at different sintering temperatures..........

Keywords - β TCP, Powder Metallurgy, Sintered structure, Shrinkage, Density, Porosity, Vicker'shardness.

[1]. Jun'an Wang and Herbert Danninger, Dry sliding wear behavior of molybdenum alloyed sintered steels, Elsevier Wear, 222 (1), 1998, 49-56.http://dx.doi.org/10.1016/S0043-1648(98)00279-8.
[2]. Torralba JM, Costa CE and Velasco F., P/M aluminum matrix composites: an overview, Journal of Materials Processing Technology, 133(1-2), 2003, 203-206. http://dx.doi. org/10.1016/S0924-0136(02)00234-0.
[3]. Dewidar MM, Yoon H-C and Lim JK., Mechanical properties of metals for biomedical applications using powder metallurgy process: a review, Metals and Materials International, 12(3), 2006, 193-206. http://dx.doi. org/10.1007/BF03027531.
[4]. Sujan Krishna Samanta and AbhijitChanda, Study On Different Characteristics Of Doped Tri Calcium Phosphate At Different Sintering Temperatures, AIP Conf. Proc., 1724, 2016, 020042-1– 020042-6. http://dx.doi.org/10.1063/1.4945162

Paper Type	:	Research Paper
Title	:	A Heuristic Accost for Cost Effective Home Appliance Designing Using Novel E-Waste Management System
Country	:	India
Authors	:	M. Panda || D. Dutta || S. Datta || A. Ghosh || J. Adhikari

Abstract: Discarded gadgets, circuits or elements of Electrical and Electronic produces e-waste. With the dynamic progress in lithography techniques and speedy innovation numerous electronic equipment are produced day by day. Unfortunately this same technological stride created mammoth 'left out electronics' and gradually generated e-waste. This is catastrophically increasing. Consequently, global warming and greenhouse effect of society has increased manifold. In order to pacify the intensity of these effects several endeavors are attempted worldwide.......

KEYWORDS - audio, cooler, e-waste, pump, switches.ent.

[1]. Chiang, S.K. "Asia: the growth engine for the world electronics industry over the next 20 years, Circuit World, Vol.27, No 4 , (2001).
[2]. A New Opportunity for Waste Prevention, Reuse, and Recycling ,United States Solid Waste and EPA 530-F-01-006 Environmental Protection Emergency Response, June 2001 Agency (5306W)
[3]. Richards, B.,Environmental Management in Electronics Manufacturing, GECMarconi Materials Technology, Hirst Division, Borehamwood, England) Circuit World Volume 23 Number 4 pp. 16-21 , (1997)
[4]. Basu, I. ,India, The E-Wasteland http:/ /www.postchronicle.com/ news/ technology/article _21219271. shtml) , on08/05/2006

Paper Type	:	Research Paper
Title	:	Design and Modeling of Hybrid CMOS SET Based Comparator for Next Generation IC
Country	:	India
Authors	:	Sanjay Bhadra || Abhishek Roy || Sumedha Chanda || Abhradeep Ghosh || MouktikBhattacharya

Abstract: A new designed structure namely Hybrid CMOS SET can conglomerate both merits of Single Electron Transistor (SET) and CMOS transistor. The authors here illustrate Hybrid CMOS SET based logic gates in designing advanced decision making Nano IC's using logic based comparator. The concept is to be incorporated in next generation electronic system and the operation is validated using Tanner environment

Keywords -Hybrid CMOS SET, SET, SED.

[1]. M. A. Kastner, "The single electron transistor and artificial atoms", Ann. Phy. (Leipzig), vol. 9, pp. 885-895, 2000. [2]AmizaRasmi&UdaHashim "Single-electron transistor (SET): Literature Review" journal 2005, Koieg University, Malaysia.
[2]. K. K. Likharev : IBM J. Res. Devel., vol 32 , 144 , 1988
[3]. Kawarabayashi, J. ;Kadoi, T. ; Watanabe, K.-I. ; Uritani, A. ; Iguchi, T., "Single electron transistor for cryogenic detector read-out", IEEE Nuclear Science Symposium Conference Record, 2001
[4]. XiaobaoChen ;Zuocheng Xing ; Bingcai Sui, "A model for energy quantization of single-electron transistor below 10nm", IEEE 9th International Conference on ASIC (ASICON), 2011.
[5]. Ono, Y. ;Takahashi, Y., "Single-electron pass-transistor logic and its application to a binary adder" Symposium on VLSI Circuits, 2001. Digest of Technical Papers. 2001.

Paper Type	:	Research Paper
Title	:	Cost Effective High Speed Hardware Modelling of VLC System with LED
Country	:	India
Authors	:	Dr. J. Gope(MIEEE) || M. Panda || A. Mukherjee || D. Biswas || P. Ghosh

Abstract: Light, rather simply removing the darkness is now used as a legendary source of communication. This manuscript discuss about the incorporation of light as a medium for data communication. Here two devices are interfaced through light without any interconnection. This proposed model describes how LED can be used as a source for data transmission and sensor for data reception.........

Keywords -VLC, Super Bright LED, Op-Amp, BJT, FSO.

[1] Bruce 1990, pg. 336
[2] M. Kavehrad, P. Amirshahi, "Hybrid MVLV Power Lines and White Light Emitting Diodes for TriplePlay Broadband Access Communications," IEC Comprehensive Report on Achieving the Triple Play: Technologies and Business Models for Success, ISBN 1931695512, pp. 167178, January 2006. See publication here (http://cictr.ee.psu.edu/research/wc/IECWhiteLEDTriplePlay.pdf)
[3] "500 Megabits/Second with White LED Light" (Press release). Siemens. Jan 18, 2010.
[4] http://www.ted.com/talks/harald_haas_wireless_data_from_every_light_bulb.html

Paper Type	:	Research Paper
Title	:	A Hypothetical Approach of Designing Novel Reversible Combinational Logic
Country	:	India
Authors	:	Dr. Jayanta Gope (MIEEE, CE) || Soumitra Mondal || Manidipa Kundu || Snigdha Chowdhury (Kolay)

Abstract: Reversible logic attained major height in the contemporary research interest by leaps and bounds due to its low power consumption like design specs. The reversible logic has commencing future in CMOS design, bioinformatics, optical information processing, cryptography and nano electronic circuits. On the other hand logic circuits for digital system perform a specific information processing operation. It is designed by a set of Boolean function.........

Keywords -Combinational Logic, Constant Input, Garbage Output, Quantum Cost, Reversible Logic Gates.

[1]. Landauer, R., 'Irreversibility and heat generation in the computing process, IBM J. Research and Development',5(3): pp. 183 191, 1961.
[2]. Bennett, C.H., 'Logical reversibility of Computational, IBM J. Research and Development', 17: pp. 525-532, 1973.
[3]. Prashant, R.Yelekar, Prof. Sujata, S. Chiwande 'Introduction to Reversible Logic Gates & its Application'
[4]. P.Vanusha, k.Amurtha Vally, ' Low Power Computing Logic Gates design using Reversible logic'
[5]. 'ISE Simulator (ISim)' UG682 (v1.0) April 27

Paper Type	:	Research Paper
Title	:	Analytical Study Of The Preposed Advanced Combined Antilock Braking System
Country	:	India
Authors	:	Dr. J.Gope (MIEEE, CE) || Arijit Bhattacharya || Anamitra Bhattacharya || Sougata Mallick || Krishnendu Bera

Abstract: Electronically Controlled Combined-ABS is a novel controlled braking system for motor vehicles. The present review is a part of analytical & numerical study that categorically involves intrinsic survey of ABS. In this present manuscript the authors limit themselves in scholastic analysis of the design of C-ABS systems only. Furthermore, MATLAB simulation tool is employed to prototype a cognizant model and a comparative study is followed then after. This happens to be a heuristic approach and it is exclusively relevant to a generic crisis. The authors advocate for the incorporation of electronically combined antilock-braking systems in future motorcycles

Keywords -C-ABS, Electronically Controlled Unit (ECU), Enhanced Safety with precise braking mechanism.

[1]. No. Of Registered Vehicles in INDIA[https://data.gov.in/catalog/total-number-registered-motor-vehicles-india].
[2]. No of road accidents during the year 2008-2011 in INDIA[https://data.gov.in/catalog/total-number-road-accidents-india]
[3]. No of accidents, deaths, etc during the year 2009-2012 in INDIA by two wheelers[https://data.gov.in/catalog/stateut-wise-total-number-road-accidents-persons-killedinjured-fatal-accidents-due-two]
[4]. Tianku Fu, "Modelling and performance analysis of ABS system with non-linear control", 2000.
[5]. Tobias Eriksson, "Co-simulation of full vehicle model in Adams and anti-lock brake system model in Simulink", 2014.

Paper Type	:	Research Paper
Title	:	Modeling of Low Cost Power Generation Unit from Waste Heat
Country	:	India
Authors	:	Debartha Catterjee || Dr. Jayanta Gope (MIEEE, CE) || Dr. A.S. Choudhury || Sirshendu Modak

Abstract: To cope up with the increasing power shortage crisis numerous attempts have been reported so far in reputed journals. But the ardent fact is that nearly 25% of the power is used as heat in actual practice and largely 75% power is wasted. The authors are keen to develop a low cost power generating model for exclusive use in rural India. A proposal for a prototype is being done here that is capable of generating power from waste heat using a TEM...........

Keywords – power generation, thermoelectric module, seebeck effect, low cost.

[1]. WHO: Household Air Pollution Findings, Global Burden of disease; 2010
[2]. WHO. Global health risks: mortality and burden of disease attributable to selected major risks; 2009.
[3]. H.J. Goldsmid. Applications of Thermoelectricity, Methuen Monograph, London, 1960.
[4]. Rowe DM, Min G. Design theory of thermoelectric modules for electric power generation. IEEE Proc-Sci 1996;143(6).
[5]. C.M. Bhandari, and D.M. Rowe, Thermal Conduction in Semiconductors, Wiley Eastern Ltd, 1988.

Paper Type	:	Research Paper
Title	:	Design of Single Electron (SEEL) Encoded Logic Based Hamming Code IC
Country	:	India
Authors	:	Dr. J. Gope (MIEEE, CE) || S. Chakraborty || I. Misra || R. Mandal || T. Chatterjee

Abstract: Digital information system do poses errors, these errors are the consequence of path delay in communication system as some sort of errored signal processing to achieve an error free information. Error detection circuits are pivoted several tropology's are being implied since the last three decade. In the past CMOS era we see how single electron transistor are incorporated to achieve error free signal..........

Keywords -CMOS, Digital information, Errors, Hamming Code, Path Delay, SEEL.

[1]. K.K. LIKHAREV, "Single-Electron Devices and Their Applications" 0018–9219/99 IEEE, PROCEEDINGS OF THE IEEE, VOL. 87, NO. 4, APRIL 1999
[2]. Sameh Ebrahim Rehan, "A Novel Half Adder using SET technology" Proceedings of the 2nd IEEE International Conference on Nano/Micro Engineered and Molecular Systems January 16 - 19, 2007, Bangkok, Thailand, 1-4244-0610-2/07.
[3]. "Addition Related Arithmetic Operations via Controlled Transport of Charge", IEEE Trans. on Computers, Vol. 54, No. 3, March 2005.
[4]. Katsuhiko Degawa Takafumi Aoki,Tatsuo Higuchi, Hiroshi Inokawa and Yasuo Takahashi, "A Single-Electron-Transistor Logic Gate Family and Its Application Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic", Proceedings of the 34th International Symposium on Multiple-Valued Logic.

Paper Type	:	Research Paper
Title	:	Single Spin Logic Based Designing of Decision Making Sub-System: A Case Study
Country	:	India
Authors	:	Dr. Jayanta Gope (MIEEE, CE) || Sarbojeet Bhowmick || Jeet Chakraborty || Amit Ghosh || Debarati Ghosal

Abstract: The quest for UTB device in post CMOS era ushered drastic change in the world of electronics. One such promising candidate is the Single Spin Logic. It forms new world of electronics that precisely depends upon the spin-pseudo effect of electron rather than the charge of an electron. Incorporating this modus the author attempted to improvise SSL technology in man-machine interface engineering. A SSL based 'Decision Making Sub-System' nano ASIC is articulated here and the same is tested for functioning.........

Keywords -Single Spin Logic, MOSFET, Fabrication technique of SSL, Logic gates, Decision Making Sub System, CMOS.

[1]. Hybrid CMOS single-electron transistor device and circuit design S.Mahapatra, AM Ionescu-2006 - dl.acm.org
[2]. H. Agarwal, S.Pramanik, S. Bandyopadhyay , "Single spin universal Boolean logic gates", IOP Publishing and Deutsche Physikalische Gesellschaft, New Journal of Physics 10 January 2008 .arvix.org/abs/0801.3979
[3]. Bandopadhyay, Supriyo, Cahay ,Marc,:‟TOPICAL REVIEW Electron spin for classical information processing: a brief survey of spin- based logic devices, gates and circuits‟, Nanotechnology 20(2009) 412001(35pp)
[4]. Spin-based logic in semiconductors for reconfigurable large-scale circuits H Dery, P Dalal, LJ Sham - Nature, 2007 - nature.com

Paper Type	:	Research Paper
Title	:	Design of A Compact, Tetra-band Frequency Selective Surface for Communication Purpose
Country	:	India
Authors	:	Riya Bhattacharyya || Priyanka Deb Sinha || PathaPratim Sarkar

Abstract: This paper presents Simulated and Experimental investigation on a compact, multi band Frequency Selective Surface using simple geometry. The designed Frequency Selective Surface consists of periodic array of Patches, where each patch has five interconnected rhombus shaped slots inside it. It's experimentally found that four bands of resonating frequencies 2.89GHz,8.14 GHz, 10.15GHZ and 11.61GHz are exhibited within the operating frequency band of the proposed FSS.........

Keywords -Frequency Selective Surface, Slot, Size Reduction, ResonatingFrequency.

[1]. J. A. Reed and D. M. Byrne, "Frequency Selective Surfaces with Multiple Apertures within a Periodic Cell", J. Opt. Soc. Am. A/ Vol. 15, No. 3/March 1998.
[2]. N.D Agrawal, W.A Imbraile,"Design of a Dichroic CassegrainSubreflector", IEEE Trans, AP-27(4), pp. 466-473, 1979.
[3]. S.W Lee et al,"Design for the MDRSS Tri Band Reflector Antenna", paper presented at the 1991 Int. IEEE AP-S Symposium, Ontario, Canada, pp. 666-669, 1991.
[4]. K. Ueno et al,"Characteristic of FSS for a Multi –Band Communication Satellite", paper presented at the 1991 Int. IEEE AP-S Symposium, Ontario, Canada, 1991.

Paper Type	:	Research Paper
Title	:	Design of Hybrid Cmos-Set Based Hamming Code Nano Ic
Country	:	India
Authors	:	Dr. J. Gope (MIEEE, CE) || S. Chakraborty || I. Misra || R. Mandal || T. Chatterjee

Abstract: e-beam' Lithography technique is a boon to the device engineers. Consequently, Single Electronic Transistors (SET), a rather new field of solid state science and technology fostered promptly in both theory and experiments. Exploration in this arena ushered promising domino effect for post CMOS era devices. In spite of copious pros of SET, the delicacy in fully exploring the 'material goods' of SET and further deploying them in new architectures to integrate them on a single chip remains a challenge........

Keywords -CMOS, Hamming Code, Lithography technique, Nano IC, Robustness, SET

[1]. K. K. Likharev : IBM J. Res. Devel., vol 32 , 144 , 1988
[2]. P. Hadley, G. Lientschnig, and M. Lai, ―Single-Electron Transistors,‖ pp. 1–8.
[3]. Haiqin Zhong ; Yaqing Chi ; He Sun ; Chao Zhang ; Liang Fang, ―Macromodeling of realistic single electron transistors for large scale circuit simulation‖, 3rd International Nanoelectronics Conference (INEC), 2010
[4]. Christoph Wasshuber "Single-Electronics – How It Works. How It's Used. How It's Simulated" – IEEE Proceedings of the International Symposium on Quality Electronic Design (ISQED.02), March 2002 pp. 502-507.
[5]. C. Wasshuber, H. Kosina, S. Selberherr, IEEE T. Comput. Aid D. 16, 937 (1997).

Paper Type	:	Research Paper
Title	:	Single Spin Wireless Architecture of nm Priority Resolver
Country	:	India
Authors	:	Dr. J. Gope (MIEEE, CE) || S. Chowdhury (Kolay) || S. Samajpati || B. Kar

Abstract: Priority resolver is ubiquitous in digital logic circuits as it is frequently used to optimize large number of inputs into a minimum number of outputs. This particular circuit exclusively demonstrate manifestation of outputs, controlled by the priority of logic interventions of the inputs. CMOS Logic made circuits with higher number of inputs experiences an excessive power dissipation. On the other hand, Single Spin Logic (SSL) offers low power dissipation, high speed, high packing density in circuit design.

Keywords -Not wired , power dissipation ,priority resolver , resolver , Single Spin Logic (SSL).

[1] Dr. Jayanta Gope et.al.,"Hybrid CMOS-SET Decision Making Nano IC: A Case Study" , International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 6, June 2015.

[2] Marc Cahay, Supriyo Bandyopadhyay, "An electron‟s spin---Part I", Potentials, IEEE, 2009.
[3] Subir Kumar Sarkar et.al., "SPINTRONICS DEVICE BASED POWER EFFICIENT VLSI CHIP DESIGN FOR UNIVERSAL CODE CONVERTER", Canadian Journal of pure & applied science, SENRA Academic Publishers, Burnaby, British Columbia,Vol.2,No.3,pp 595-600,2008,IISN: 1715-9997.

[4] H. Agarwal et.al.,"Single spin universal Boolean logic gates", IOP Publishing and Deutsche Physikalische Gesellschaft, New Journal of Physics, volume 10,January 2008.

Paper Type	:	Research Paper
Title	:	Hypothetical Modelling of SRAM Using Spin Degree of Freedom
Country	:	India
Authors	:	J. Gope (MIEEE, CE) || S. Chowdhury (Kolay) || S. Chakraborty || M. Sihgha

Abstract: Consequence of electron mobility is a pivotal study in low power consuming device research. Single Spin Logic (SSL) is an optimal solution derived from Spintronics that also usher a new horizon in device research, without tangling over the only charge of an electron. It resonates the notion of spin degree of freedom and the vicinity of electron coherence. Thus.......

Keywords -SSL, Spintronics, Decoder, D flip flop, Static Random Access Memory (SRAM).

[1] Dr. Jayanta Gope et.al., "Hybrid CMOS-SET Decision Making Nano IC: A Case Study" , International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 6, June 2015

[2] Marc Cahay, Supriyo Bandyopadhyay, "An electron‟s spin---Part I", Potentials, IEEE, 2009.
[3] Subir Kumar Sarkar et.al., "SPINTRONICS DEVICE BASED POWER EFFICIENT VLSI CHIP DESIGN FOR UNIVERSAL CODE CONVERTER", Canadian Journal of pure & applied science, SENRA Academic Publishers, Burnaby, British Columbia,Vol.2,No.3,pp 595-600,2008,IISN: 1715-9997..

[4] H.Agarwal et.al. ,"Single spin universal Boolean logic gates", IOP Publishing and Deutsche Physikalische Gesellschaft, New Journal of Physics, volume 10,January 2008.

Paper Type	:	Research Paper
Title	:	Maximum Watt Margin (MWM) of Different Buses of a Multibus System
Country	:	India
Authors	:	Sourav Basu || Sourav Debnath

Abstract:The purpose of this paper is to examine the Maximum Watt Margin (MWM) of different buses of a multi-bus system. Load Flow analysis is carried out by using Newton Raphson iterative method and the weakest and the strongest buses are determined by using ∂Qi/∂Vi index. A study is also performed to observe the variation of Maximum Watt Margin (MWM) with the degree of weakness of the bus. P-V and Q-V profiles are observed and reported. The whole method is tested on the IEEE-57 bus system and the observations are revealed in this paper.

Keywords -Loadability, Maximum Watt Margin (MWM), ∂Qi/∂Vi index, Strongest Bus, Weakest Bus.

[1] Sourav Basu, Chandramouli Gupta, Sumana Chowdhuri- "Voltage Stability Margin (VSM) and Maximum Loading Point (MLP) Of A Multi-Bus System Before and After Compensation", International Journal of Engineering Research and Development, Vol-5, Issue-7, pp-30-35, January 2013.
[2] Kabir Chakraborty and Sangita Das Biswas "An Offline Simulation Method to Identify the Weakest Bus and Its Voltage Stability Margin in a Multi-bus Power Network", Proceeding of International Conference MS'07, India, December 3-5,2007, pp. 1-5.
[3] An Analytical Investigation of Voltage Stability of an EHV Transmission Network based on Load Flow-A. Chakrabarti and P. Sen, Journal of Electrical Engg., Institution of Engg. (I, Vol.-76, May 1995].
[4] P. Kessel and H. Glavitsch "Estimating the Voltage Stability of Power System" IEEE Trans. On Power delivery, Vol. PWRD-1, No.3 July/1986, pp. 346-354.