iosr-JVSP   Volume-9 ~ Issue-4 ~ July-August 2019

ABSTRACT: The speed of Content-Addressable Memories (CAMs), here the content is an image data or image feature, is a kind of struggle to logical processors data. The processor architecture must also have increasing capabilities to cope with the fast computational algorithms, data storage and sensing, content detection and diagnosis and improved search based memory designs. The focus of this work is fast computations and search based designs for CAMs. Proposed EB-CAM will be analyzed using IC design tools in 90nm technology, using Verilog hardware description language and usage of Cadence for layout generation and parasitic extraction of the circuit components.

Keywords- Image analysis, Feature Learning, Content-Addressable Memory, Processor Hardware, High Speed, Low Power, Pattern Search, Parallel Registers

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ABSTRACT: In this paper we introduced a design and essential learning process basic in Quantum dot cellularautomata(QCA) and Reversible logic gates using QCA. QCA it is nanoscale computing technology that can represents binary information using spatial distribution of electrons.It has features like extremely small feature size, and high clock frequency make QCA an attractive solution for implementing nano-scale architectures. The power dissipation is the main limitation of all Nano electronics including QCA. The Reversible computing is considered as the reliable solution for power dissipation. The realization of quantum computation is not possible without reversible logic also, the Information's are not loss in reversible circuits. Reversal gates are the main building blocks for reversible circuits.

Keywords- Cellular Automata(CA), Reversible Gates, Reversible logic ,Quantum Computer(QC),Quantum dotcellular automata(QCA).

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[4]. Lukac, Martin, et al. "Evolutionary approach to quantum and reversible circuits synthesis." Artificial Intelligence Review 20.3-4 (2003): 361-417.
[5]. Morita, Kenichi. "Reversible computing and cellular automata—A survey." Theoretical Computer Science 395.1 (2008): 101-131.

ABSTRACT: In this brief, a new positive feedback comparator design is proposed. The comparator plays an important role in the electronic circuits and these are used to compare two input signals and to produce the one output signal. A low-power two stage dynamic comparator is an advanced comparator and it contains PMOS transistors are used at the input of the first and second stages of the comparator. It reduces the power consumption by a factor of two, to achieve a controllable pre-amplifier gain. This comparator leads to increase in delay and transistor count. To overcome this problem a positive feedback comparator is proposed. This Positive feedback comparator is having lower power consumption and less propagation delay compared to existing low power two stage dynamic comparator. The backend simulations are achieved by using MENTOR GRAPHICS in 130nm technology and frontend simulations are done by using XILINX.

Keywords- Pre-amplifier gain, Dynamic comparator, Low-power two stage dynamic comparator, Positive feedback comparator, Mentor graphics, Xilinx

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ABSTRACT: In this brief, a new Comparator based Domino logic design is proposed. The Comparator technique is used to compare the voltages and the Domino logic technique is used to implement the logic function. In the existing system, The different domino logic techniques are designed for wide fan-in gates. The Foot Driven Stack transistor domino logic technique is one of the existing method. This leads to increase in delay . To overcome this problem a Comparator based domino logic is proposed. This Comparator based domino logic is having lower power consumption and low propagation delay than existing domino logic circuits. The backend simulations are achieved by using MENTOR GRAPHICS in 130nm technology and frontend simulations are done by using XILINX..

Keywords- Digital circuits, ,High speed domino gate, Low power VLSI circuit, Wide fan-in gates, Comparator based domino logic gate, Mentor graphics,Xilinx

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ABSTRACT: In the recent decade discrete wavelets have become very popular in Digital Signal Processing area due to their capability of simultaneous representation of time-frequency information of a signal. Wavelet transform is especially very important for processing non-stationary signals. Due to the high demand for real time DSP hardware architectures the demand for high throughput and low power in portable devices requires discrete wavelet hardware implementation also to be efficient. In this research three different advanced polyphase architectures for wavelet filter banking are implemented. Xilinx Artix-7 FPGAs are used for implementation through Vivado 2015.2 design suite. The programming is done using Verilog Hardware Description Language (HDL)...

Keywords- Discrete Wavelets, Wavelet Filter Banks, FPGA, Verilog HDL

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