ABSTRACT: This work presents the functionality of some unique Schmitt trigger circuits designed on the basis of the impact of load capacitance and supply voltages together with hysteresis width, propagation delay and average power dissipation. All the simulation results are performed for 0.18 μm CMOS process technology. It is found that through the recommended design a larger hysteresis width can be attained by modifying the arrangement and organization of transistors as well as the ratio of width to length of channel. The results of our analysis reveal that the designed Schmitt trigger can be driven using low voltage of 0.8-1.5 V and the power dissipation is reduced to only 47.24 pW. The total active area of our suggested trigger circuit is 10.80 × 10.65 μm2. The proposed Schmitt trigger will be suitable and useful where large hysteresis width is required to improve the noise margin. Therefore, it may be propounded that our designed Schmitt trigger have low power dissipation, large hysteresis width and plausibly be operated with lower voltage compared to earlier designs found in literature.
Key Words: Schmitt trigger; Hysteresis width; Power dissipation; Propagation delay
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