iosr-JVSP   Volume-11 ~ Issue-3 ~ May - Jun. 2021

ABSTRACT: This work presents the functionality of some unique Schmitt trigger circuits designed on the basis of the impact of load capacitance and supply voltages together with hysteresis width, propagation delay and average power dissipation. All the simulation results are performed for 0.18 μm CMOS process technology. It is found that through the recommended design a larger hysteresis width can be attained by modifying the arrangement and organization of transistors as well as the ratio of width to length of channel. The results of our analysis reveal that the designed Schmitt trigger can be driven using low voltage of 0.8-1.5 V and the power dissipation is reduced to only 47.24 pW. The total active area of our suggested trigger circuit is 10.80 × 10.65 μm2. The proposed Schmitt trigger will be suitable and useful where large hysteresis width is required to improve the noise margin. Therefore, it may be propounded that our designed Schmitt trigger have low power dissipation, large hysteresis width and plausibly be operated with lower voltage compared to earlier designs found in literature.

Key Words: Schmitt trigger; Hysteresis width; Power dissipation; Propagation delay

[1]. V. Katyal, R. L. Geiger, D. J. Chen, "Adjustable hysteresis CMOS Schmitt triggers," IEEE International Symposium on Circuits and Systems, Seattle, WA, 1938–1941, 2008, doi:10.1109/ISCAS.2008.4541823.
[2]. H. Rashid, M. Mamun, M. S. Amin; and H. Husain, "Design of a Low Voltage Schmitt Trigger in 0.18um CMOS Process With Tunable Hysteresis", Modern Applied Science, 7(4), 47–54, 2013, doi:10.5539/mas.v7n4p47.
[3]. J. B. Kuang and C. T. Chuang, "PD/SOI CMOS Schmitt trigger circuits with controllable hysteresis," 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517), 283–286, 2001, doi: 10.1109/VTSA.2001.934540.
[4]. N. H. E. Weste, D. Harris, and A. Bannerjee, CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition). Pearson Education Inc., 2006.
[5]. M. Stayaert, and W. Sansen, "Novel CMOS Schmitt trigger", Electronic Letters, 22(4), 203–204. 1986.

ABSTRACT: In today's high performance advanced VLSI circuit design including most semicustom design gives efficient utilization of circuit resources with better productivity offering a good layout density and high performances with optimum resources in submicron designs. The main idea is to divide the processor into small partitions called Functional Unit Block (FUB) based on the different functionalities of the processor like Execution, Memory, Fetch, Decode and Out of order. The major focus of this work is to optimize the FUB in terms of timing, power and area. With the enhancement of the existing design technology and optimization methods, new design technology called datapath design is used to deliver a quality design and this work also proposes various logical optimization.....

Key Words: datapath;synthesis;optimization;timing;clock tuning;

[1]. Linumon Thomas and Kiran V, "Timing Convergence Techniques in Digital VLSI Designs"
[2]. Mohamed Khalil Hani and Nasir Shaikh-Husin, "Simultaneous Routing and Buffer Insertion Algorithm for Interconnect Delay
Optimization in VLSI Layout Design"
[3]. Narendra Shenoy, Mahesh Iyer, Robert Damiano, Kevin Harer and Hi-Keung Ma ,"A Robust Solution to the Timing Convergence
Problem in High-Performance Design," ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 306-
324, April 2006
[4]. http://www.intelpedia.intel.com

ABSTRACT: Half-unit-biased (HUB) is a new design that is based on the displacement of the digits represented by half the unit last performed. This arrangement makes the two's complement and round operations closest by avoiding any carry propagation. This saves energy, time and area consumption. Given that the IEEE floating point standard uses unbiased rounding as the default mode, this feature is also desirable for HUB approaches. In this article, we study unbiased rounding for HUB floating point addition both within independent operation and within FMA. We show two different options to eliminate bias by eliminating the sum results either partially or completely. Implementation results of the proposed architecture to help designers decide what their best option.

Keywords: HUB format, unbiased rounding, Floating point , IEEE

[1]. E. Alpaydin, Machine learning : the new AI, 2016.
[2]. M. Kubat, An Introduction to Machine Learning, 2015, no. August.
[3]. J. A. Stankovic, "Research directions for the internet of things," IEEE Internet of Things Journal, vol. 1, no. 1, pp. 3–9, Feb 2014.
[4]. F. K. Shaikh, S. Zeadally, and E. Exposito, "Enabling technologies for green Internet of Things," IEEE Systems Journal, vol. PP, no. 99, pp. 983–994, Jun 2015.
[5]. R. Murphy, T. Sterling, and C. Dekate, "Advanced architectures and execution models to support green computing," Computing in Science and Engineering, vol. 12, no. 6, pp. 38–47, Nov 2010.

ABSTRACT: The aim of this project, was to compress audio data in such a way so that the quality was preserved but was given at a lower bit rate, utilizing a PIC32 microcontroller. The speech compression algorithm used is known as adaptive differential pulse code modulation or ADPCM. The ADPCM algorithm can be broken down into two major components, the encoding process and the decoding process. In an effort to give audio capabilities to a microcontroller, a C implementation of a simplified ADPCM algorithm was developed and programmed onto the PIC32. During the testing phase, the C implementation for the PIC32 was compared to a working MATLAB implementation of the same algorithm, in order to confirm the numerical data was the same throughout the compression process. Once both the encoding and decoding processes produced identical outputs in both C and MATLAB, the code was put onto the microcontroller. The result was that audio compression was successful; the spectral content of the raw speech data and compressed speech data are the same and the entire process only used 1/5 of the CPU of the PIC32.

Key Word: Digital Signal Processing, Adaptive Pulse Code Modulation, Microcontroller

[1]. https://www.mathworks.com/matlabcentral/fileexchange/6480-adpcm-encoder-and-decoder?focused=5056015&tab=function
[2]. Adaptive differential pulse-code modulation http://en.wikipedia.org/wiki/Adaptive_differential_pulsecode_modulation
[3]. Pulse-code modulation http://en.wikipedia.org/wiki/Pulse-code_modulation
[4]. DPCM https://supportforums.cisco.com/docs/DOC-1423 [4] AVR336: ADPCM Decoder http://atmel.com/dyn/resources/prod_documents/doc2572.pdf
[5]. Using the ADPCM Algorithm in Dialogic® Voice Processing http://www.dialogic.com/~/media/products/docs/appnotes/10532_Dialog ic _ADPCM_Algorithm_an.pdf

ABSTRACT: Principle objective of Image enhancement is to process an image so that result is more suitable than original image for specific application. Digital image enhancement techniques provide a multitude of choices for improving the visual quality of images. Appropriate choice of such techniques is greatly influenced by the imaging modality, task at hand and viewing conditions. The paper focuses on techniques for image enhancement.

Keywords: Digital, Image Processing, Image Enhancement

[1]. Bhabatosh Chanda and Dwijest Dutta Majumder, 2012, Digital Image Processing and Analysis.
[2]. R.W.Jr. Weeks,(2012). Fundamental of Electronic Image Processing . Bellingham: SPIE Press
[3]. A. K. Jain, Fundamentals of Digital Image Processing. Englewood Cliffs, NJ: Prentice Hall, 2013.
[4]. R.M. Haralick, and L.G. Shapiro, Computer and Robot Vision, Vol-1, Addison Wesley, Reading, MA, 2012.
[5]. R. Jain, R. Kasturi and B.G. Schunck, Machine Vision, McGraw-Hill International Edition, 1995.

ABSTRACT: Increasing complexity of VLSI designs makes it hard to follow fine details within a large design. Especially in variability studies it is important to be able to determine for example, edge lengths in the x and y direction of mask shapes, within a device or a circuit. The line-edge roughness variation vs. length scales within the circuit is valuable information for the effects of variability of circuit performance. In the current article a simulation flow is presented to help circuit designer, gain more understanding of the fabricated features of their circuits. Is starts from mask files in CIF format and decomposes them into their corresponding layers in order to be used in electron-beam-lithography simulations, stochastic-lithography simulation and line width roughness metrology studies. The code is integrated in a complete software suite

Keywords: Matlab, VLSI, layout, CIF, electron-beam lithography, stochastic-lithography, roughness, metrology

[1]. https://en.wikipedia.org/wiki/Common_Intermediate_Format
[2]. G.P. Patsis, Ν. Glezos, Electron-beam lithography simulation for EUV mask applications, Journal of Physics: Conference Series, 10 (1), 2005, 385-388.
[3]. G. P. Patsis, N. Tsikrikas, I. Raptis, N. Glezos, Electron-beam lithography simulation for the fabrication of EUV masks, Microelectronic Engineering, 83 (4-9 SPEC. ISS.), 2006, 1148-1151.
[4]. G. P. Patsis, M. D. Nijkerk, L. H. A. Leunissen, E. Gogolides, Simultation of material and processing effects on photoresist lineedge roughness, International Journal of Computational Science and Engineering, 2 (3-4), 2006, 134-143.
[5]. G. P. Patsis, V. Constantoudis, A. Tserepi, E. Gogolides, Quantification of line-edge roughness of photoresists. I. A comparison between off-line and on-line analysis of top-down scanning electron microscopy images, Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 21 (3), 2003, 1008-1018.