IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Current Issue Vol2-Issue4

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Paper Type : Research Paper
Title : Medical Image Compression Using Wavelets
Country : India
Authors : K. Gopi, Dr. T. Rama Shri
: 10.9790/4200-0240106      logo

ABSTRACT: With the development of CT, MRI, PET, EBCT, SMRI etc, the scanning rate and distinguishing rate of imaging equipment is enhanced greatly. Using wavelet technology, medical image can be processed in deep degree by denoising, enhancement, edge extraction etc, which can make good use of the image information and improve diagnosing. Compressions based on wavelet transform are the state-of-the-art compression technique used in medical image compression. For medical images it is critical to produce high compression performance while minimizing the amount of image data so the data can be stored economically. Modern radiology techniques provide crucial medical information for radiologists to diagnose diseases and determine appropriate treatments. Such information must be acquired through medical imaging (MI) processes. Since more and more medical images are in digital format, more economical and effective data compression technologies are required to minimize mass volume of digital image data produced in the hospitals. The wavelet-based compression scheme contains transformation, quantization, and lossless entropy coding. For the transformation stage, discrete wavelet transform and lifting schemes are introduced. In this paper an attempt has been made to analyse different wavelet techniques for image compression. Hand designed wavelets considered in this work are Haar wavelet, Daubechie wavelet, Biorthognal wavelet, Demeyer wavelet, Coiflet wavelet and Symlet wavelet. These wavelet transforms are used to compress the test images competitively by using Set Partitioning In Hierarchical Trees (SPIHT) algorithm. SPIHT is a new advanced algorithm based on wavelet transform which is gaining attention due to many potential commercial applications in the area of image compression. The SPIHT coder is also a highly refined version of the EZW algorithm.

Keywords – Wavelet, Medical Image, Compression, PSNR

[1] I. JTC1/SC29/WG1, "JPEG 2000 – lossless and lossy compression of continuous- tone and bi-level still images", Part 1: Minimum decoder. Final committee draft, Version 1.0., March 2000.
[2] G.Wallace, "The JPEG still picture compression standard", IEEE TCE, 38, 1992.
[3] Independent JPEG Group, version 6a:
[4] G. K. Wallace, "The JPEG still picture compression standard", in IEEE Transactions on Circuits and Systems for Video Technology, vol. 6, June 1996.
[5] O. K. Al-Shaykh, "JPEG-2000: A new still image compression standard", in Conference Record of Thirty-Second Asilomar Conference on Signals Systems and Computers, vol. 1, pp. 99-103, 1998.
[6] JPEG2000,
[7] Moving Picture Expert Group Standard, http://www.mpeg. org/MPEG/index.html.
[8] W. Sweldens, 1997, "The lifting scheme: A construction of second generation wavelets", SIAM J. Math. Anal., Vol.29 (2), pp.511–546.
[9] I. Daubechies, W. Sweldens, 1998, "Factoring wavelet into lifting steps", J. Fourier Anal. Appl., Vol.4 (3), pp.247–269.
[10] Daubechies I., Orthonormal bases of compactls] supported wavelets, Comm.Pure Appl. Math. 41, 909-996 (1988)

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Paper Type : Research Paper
Title : Binary Step Size Variations of LMS and NLMS
Country : India
Authors : C Mohan Rao, Dr. B Stephen Charles, Dr. M N Giri Prasad
: 10.9790/4200-0240713    logo

ABSTRACT:Due to its ease of implementation, the least mean square (LMS) algorithm is one of the most wellknown algorithms for mobile communication systems. However, the main limitation of this approach is its relatively slow convergence rate. In this paper two new variable step size Least Mean Square (LMS) adaptive filter algorithms are proposed. In the first algorithm two step sizes will be calculated from two values which will vary iteration to iteration. This algorithm is analogous to LMS algorithm, and produces better convergence performance compared to that of LMS. In the second algorithm also two step sizes are calculated based on a variable. This algorithm is analogous to Normalised Least Mean Square (NLMS) and produces better convergence performance compared to that of NLMS.

Keywords –LMS, NLMS, Binary Step, Channel Equalization.

[1] W.-P. Ang, B. Farhang-Boroujeny, "A new class of gradient adaptive step-size LMS algorithms". IEEE Trans. Signal Process. 49, 805–810 (2001).
[2] C. Gazor, "Predictions in LMS-type adaptive algorithm for smoothly time-varying environments". IEEE Trans. Signal Process. 47, 1735–1739 (1999).
[3] D.G. Manolakis, V.K. Ingle, M.S. Kogan, "Statistical and Adaptive Signal Processing", McGraw-Hill, New York, 2000.
Binary Step Size Variations of LMS and NLMS 13 | Page
[4] L.C. Godara, "Applications of array antenna to mobile communications, Part I: Performance improvement, feasibility, and system considerations". Proc. IEEE 85, 1031–1060 (1997).
[5] L.C. Godara, "Applications of array antenna to mobile communications, Part II: Beam forming and direction-of-arrival considerations". Proc. IEEE 85, 1195–1238 (1997).
[6] S. Haykin, "Adaptive Filter Theory", Prentice Hall, New York, 1995.
[7] J.H. Winters, "Signal acquisition and tracking with adaptive arrays in the digital mobile radio system IS-54 with flat fading". IEEE Trans. Veh. Technol. 42, 377–384 (1993).
[8] J.H. Winters, "Smart antenna for wireless systems". IEEE Pers. Commun. 23–27 (1998).
[9] V. Solo, X. Kong, "Adaptive Signal Processing Algorithms: Stability and Performance", Prentice Hall, New York, 1995.
[10] Bernard Widrow and Marcian E. Hoff, "Adaptive Switching Circuits", IRE Wescon Convention Record, 1960.

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Paper Type : Research Paper
Title : Image Reconstruction Using Discrete Wavelet Transform
Country : Inda
Authors : G.Shruthi , Radha Krishna A.N.
: 10.9790/4200-0241420      logo

ABSTRACT: In the recent growth of data intensive and multimedia based applications, efficient image compression solutions are becoming critical. The main objective of Image Compression is to reduce redundancy of the data and improve the efficiency. The main techniques used are Fourier Analysis, Discrete Cosine Transform vector quantization method, sub-band coding method. The drawbacks in the above methods are, they cannot be used for real time systems. In order to overcome these problems, the Wavelet Transform method has been introduced. Wavelet Analysis is highly capable of revealing aspects of data like trends, breakdown points, discontinuities in higher derivates and self similarity and can often compress or diagnose a signal without appreciable degradation. Here, we implement a lossy image compression technique using Matlab Wavelet Toolbox and Matlab Functions where the wavelet transform of the signal is performed, then calculated a threshold based on the compression ratio acquired by the user.

Keywords : CWT, DWT, Decomposition,, Haar Transform, Lossy Compression, Wavelet.

[1]. Aboufadel, Edward. Discovering Wavelets, by Edward Aboufadel and Steven Schliker. New York; Chichester : Wiley, 1999
[2]. Hubbard, Barbara Burke. The World According to Wavelets. A.K Peters Ltd, 1995.
[3]. Rudra Pratap, Getting started with MATLAB.
[4]. Rafael C.Gonzalez , Richard E. Woods,Digital Image processing.
[5]. Chrysafis, Christos and Ortega, Antonio. Line-Based, Reduced Memory, Wavelet Image Compression. Buccigrossi, Robert W. and Simoncelli, Eero P. Image Compression via Joint Statistical Characterization in the Wavelet Domain
[6]. Chambolle, Antonin et. al. Nonlinear Wavelet Image Processing Variational Problems, Compression and Noise Removal Through Wavelet Shrinkage
[7]. Usevitch, Bryan E. A Tutorial on Modern Lossy Wavelet Image Compression: Foundations of JPEG 2000..
[8]. Adams, Michael D. and Kossentini, Faouzi. Reversible Integer-to-Integer Wavelet Transforms for Image Compression: Performance Evaluation and Analysis
[9]. Antonini, Marc et. al. Image Coding Using Wavelet Transform.
[10]. S. Jaffard, Y. Meyer, and R. D. Ryan, Wavelets: Tools for Science & Technology, SIAM, Philadelphia.

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Paper Type : Research Paper
Title : Charge Pump, Loop Filter and VCO for Phase Lock Loop Using 0.18μm CMOS Technology
Country : India
Authors : Kashyap K. Patel, Nilesh D. Patel , Kruti P. Thakore
: 10.9790/4200-0242125      logo

ABSTRACT: This paper presents a Low power charge pump, second order low pass filter and voltage controlled oscillator for low power phase lock loop. The paper contains the detailed circuit diagram of charge pump, loop filter and voltage control oscillator with 1.8v power supply. The design has been realized using 0.18um CMOS technology. Here current starved voltage control oscillator is use for phase lock loop.

Keywords: - charge pump, second order low pass filter, voltage control oscillator

[1] Kashyap K. Patel, Nilesh D. Patel, " Phase Frequency Detector and Charge Pump For DPLL Using 0.18μm CMOS Technology" International Journal of Emerging Technology and Advanced Engineering , ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3 Issue1, Page No. 55-58, January 2013)
[2] Kruti P. Thakore, Harikrishna C. Parmar, Dr.N.M. Devashrayee, " High Speed PFD with Charge Pump and Loop Filter for Low Jitter and Low Power PLL", IJECT Vol. 2, Issue 2, June 2011
[3] Urvi M. Darji, Prof. Shruti Oza, "Low Power And Low Jitter Phase Frequency Detector For DPLL Using 0.18μm CMOS Technology"
[4] Kruti P. Thakore, Dr. D. J. Shah " Design and Implementation of Low Power and Low Jitter PLL "Laljibhai Chaturbhai Institute of Technology" Bhandu-384120, 13-14, April-2012
[5] Amr M. Fahim, "A Compact, Low-Power Low-Jitter Digital PLL"
[6] Darji Urvi M. "Design, Analysis and implementation of DPLL using 0.18μm CMOS Technology " Gujarat Technological University May-June 2012
[7] Jonathan Cheung, "Low Jitter Phase-Locked Loop"

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Paper Type : Research Paper
Title : FPGA Implementation for Image Processing Algorithms Using Xilinx System Generator
Country : India
Authors : Neha. P. Raut , Prof.A.V.Gokhale
: 10.9790/4200-0242636      logo

ABSTRACT: The paper presents information about FPGA implementation for various Image Processing Algorithms using the most efficient tool called Xilinx System Generator (XSG) for Matlab. System Generator is a DSP design tool from Xilinx that enables the use of the Math Works model-based Simulink design environment for FPGA design. In this paper various morphological and intensity image processing algorithms for negatives, image enhancement, threshold,, contrast stretching, Edge detection, boundary extraction for grayscale and color images are explored. Use of Xilinx system generator for image processing effectively reduces intricacy in structural design also provides additional feature for hardware co-simulation

Index Terms—FPGA Implementation, Xilinx System Generator, Matlab, Simulink, Co-simulation.

[1] R.C. Gonzalez, R.E. Woods, "Digital Image Processing".New Jersey: Prentice-Hall 2008 v. [2] DSP System Generator User guide release 12 .1.
[3] Xilinx System Generator User's Guide, , www.Xilinxforum.
[4] Matlab Website : ,http:// [5] White paper: Using System Generator for SystematicHDL Design, Verification, and Validation WP283(v1.0) January 17, 2008 [6] Tutorial - Using Xilinx System Generator 13.2 for Co-Simulation on Digilent NEXYS3 (Spartan-6) BoardAhmed Elhossini February 22, 2013 [7] International journal of mathematical models and methods in applied sciences " Architecture for filtering images using Xilinx System Generator ‟Alba M. Sánchez G., Ricardo Alvarez G., Sully Sánchez G.; FCC and FCE BUAP [8] International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011 DOI : 10.5121/vlsic.2011.2409 95 , An Efficient Fpga Implementation Of Mri Image Filtering And Tumour Characterization Using Xilinx System Generator By Mrs.S.Allin Christe, Mr.M.Vignesh, Dr.A.Kandaswamy
[9] IJCSI International Journal of Computer Science Issues, Vol. 9, Issue 2, No 2, March 2012 ISSN (Online): 1694-0814 Hardware Software co-simulation for Image Processing Applications, A.C.Suthar, Mohammed Vayada,C.B.Patel,G.R.Kulkarni.

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Paper Type : Research Paper
Title : Open-Source 32-Bit RISC Soft-Core Processors
Country : India
Authors : Rahul R.Balwaik, Shailja R.Nayak, Prof. Amutha Jeyakumar
: 10.9790/4200-0244346      logo

ABSTRACT: A soft-core processor build using a Field-Programmable Gate Array (FPGA)'s general-purpose logic represents an embedded processor commonly used for implementation. In a large number of applications; soft-core processors play a vital role due to their ease of usage. Soft-core processors are more advantageous than their hard-core counterparts due to their reduced cost, flexibility, platform independence and greater immunity to obsolescence. This paper presents a survey of a considerable number of soft core processors available from the open-source communities. Some real world applications of these soft-core processors are also discussed followed by the comparison of their several features and characteristics. The increasing popularity of these soft-core processors will inevitably lead to more widespread usage in embedded system design. This is due to the number of significant advantages that soft-core processors hold over their hard-core counterparts.

Keywords: Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), open-source, soft-core processors.

[1] Turley. J (2005), Survey: Who uses custom chips, Embedded Systems Programming, vol. 18, no. 8, Aug.
[2] I. Kuon and J. Rose (2006), Measuring the gap between FPGAs and ASICs, in Proc. FPGA, pp. 21–30.
[3] SecretBlaze. [Online]. Available:
[4] L. Barthe, L. V. Cargnini, P. Benoit and L. Torres (2011), The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft- Core Processor, 25th IEEE International Parallel & Distributed Processing Symposium, May 16-20, Anchorage (Alaska) USA, pp. 310-313.
[5] LatticeMico32 Website:
[6] Aeroflex Gaisler (2010), SPARC V8 32-bit Processor LEON3 / LEON3-FT Companion Core Data Sheet, March, Version 1.1.
[7] Julius Baxter and Damjan Lampret (2011), OpenRISC 1200 IP Core Specification (Preliminary Draft), January, Version 0.11.
[8] Website:, June 2006.
[9] Stephen Craven, Cameron Patterson, and Peter Athanas (2005), Configurable soft processor arrays using the openfire processor, 8th Annual Conference on Military and Aerospace Programmable Logic Devices, Washington, DC, September, MAPLD.
[10] Shawn Tan Ser Ngiap (2007), AEMB 32-bit Microprocessor Core Datasheet, November.

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Paper Type : Research Paper
Title : On-Chip Techniques for Electromagnetic Interference (EMI) reduction
Country : Bangladesh
Authors : Monirul Islam, Rajib Imran, Bushra Mahjabeen
: 10.9790/4200-0244752      logo

ABSTRACT: In modern days, integrated circuits are facing different challenges with its high speed features. One of the big challenges is EMI emission from electronic devices. Different regulatory bodies like US (FCC), EN etc have strict regulations aim at limiting the amount of EMI radiations. On the designer's point of view, these effects can range from a simple degradation of a specific signal to a total loss of data. To increase chip performance the clock speed is needed to be increased which gives rise to EMI immensely, however different approaches in the design cycle can successfully limit the emission at an expected level. This paper analyses different approaches for significant low cost reduction mechanisms. For higher data rates like 8 GT/s or 16 GT/s- Clock scrambling, Clock dithering, spread spectrum clocking, differential clocking and using clock buffers etc are the most beneficial methods especially for the faster System on Chip (SoC).

Keywords- EMI, Clock scrambling, spread spectrum, EMI emissions, EMI reduction, Dithering Ckt etc.

[1] Cornelis D. Hoekstra, Frequency Modulation of System Clocks for EMI Reduction, Hewlett-Packard Journal, Article 13, August, 1997.
[2] Dr. Sergiu Radu, An Overview of Chip Level EMC Problems, Sun Microsystems, Inc.
[3] Design for EMI, Intel , Application note AP-589, February 1999.
[4] Cameron Katrai, Chris Arcus,, EMI Reduction Techniques, Pericom Semiconductor Corporation, Application Note 11, 1998, 59-64.
[5] Timing-Safe™ Spread Spectrum EMI Reduction, ON Semiconductor, P3P623S05A/B and P3P623S09A/B, July, 2010.
[6] Understanding Radiated EMI, Applications Engineering Group, MCU Division, Silicon Labs.
[7] D.J.Prasad kumar, B.Chinna rao, P.M.Francis, A Novel Techniques to Reduce EMI Attenuation by Triangular Modulation, International Journal of Engineering Research & Technology (IJERT), Vol. 1 Issue 6, August , 2012.
[8] Sachio Hayashi, Masaaki Yamada , EMI Noise Analysis under ASIC design Environment, DA Development Dept., Semiconductor DA & Test Engineering Centre, Toshiba Corporation.
[9] Subramaniam Venkatraman, Matthew Leslie, Novel spread spectrum clock generator.

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Paper Type : Research Paper
Title : Design and Implementation of Feasible Direct Digital Synthesizer to Eliminate Manual Tweaking
Country : India
Authors : Snehal Gaikwad, Kunal Dekate
: 10.9790/4200-0245356      logo

ABSTRACT: This paper presents design and simulation of the programming model of optimal and feasible Direct Digital Synthesizer that eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in analog synthesizer solutions. A Direct Digital Synthesizer is a measure part o Digital Down Converter where the DDC (Digital Down converter) has become a cornerstone technology in communication systems. Digital Down Converter (DDC) is key component of RF systems in communications, sensing, and imaging. This paper also evaluates the performance of DDS under various programming parameters and finally performs the realization of DDS using Virtex II Pro.

Keywords: Theory of DDC, Direct Digital Synthesizer (DDS), Performance of Direct Digital Synthesizer and Simulation Results

[1] Xilinx LogiCORE, Digital Up Converter (DUC) v1.4, DS276 May 23, 2005

[2] Lattice Semiconductor Corporation, The FPGA as a Flexible and Low-Cost Digital Solution for Wireless Base Stations, A Lattice Semiconductor White Paper, March 2007.

[3] Matthew P. Donadio, CIC Filter Introduction, For Free Publication by Iowegian,, 18 July 2000. [4] Pavel KOVAR, Generation of the Narrow Band Digital Modulated Signals Using Quadrature Digital Up Converter, RADIO ENGINEERING, VOL. 12, NO. 1, APRIL 2003.

[5] Direct digital synthesis (DDS) http://www.radioelectronics com/info/receivers/synth_basics/dds.php. [6] QAN19 Modulating Direct Digital Synthesizer in a quick logic FPGA . (Accessed on April 10, 2006.)

[7] Eva Murphy and Colm Slattery, All about Direct Digital Synthesis, Analog dialogue 38-08, August 2004,

[8] Xilinx LogiCORE, Multiply Accumulator v4.0, DS336 April 28, 2005 [9] Cyril Prasanna Raj P and Subash, SASTech Journal, Vol 4. PP 33-39, September 2006.

[10] S. Signell, T. G. Kouyoumdjiev, K. H. Mossberg, Design and Analysis of Bilinear Digital Ladder Filters, IEEE Trans. on Circuits and Systems, Vol. 43, No. 2. February 1996.