ABSTRACT:A low cost design and simple to implement, CMOS NP Domino logic is presented. The NP Domino logic designs require fewer transistors and are compatible with full Domino logic. The performance of NP Domino logic is also better compared to the standard Domino logic implementations. Dynamic domino logic are very good but had many challenges like monotonicity, leakage, charge sharing and noise problems. These problems are totally eliminated in the CMOS NP Domino logic (which is also known as Zipper circuits) without any penalty in performance or silicon area utilization. This paper compares NP Domino logic with static CMOS and domino (dynamic) logic design implementations.
Keywords - CMOS, NP Domino logic, monotonicity, Zipper, static,
[1] Y. Berg an O. Mirmotahari: "Ultra Low-Voltage and High Speed Dynamic and Static Precharge logic", In Proc. of the 11 th Edition of IEEE Faible Tension Faible Consommation. June 6-8, 2012, Paris, France.
[2] Lee, Charles M., and ellen W. Szeto. "Zipper CMOS". IEEE Circuit and Device Magazine, 8755-3996/86/0500-0010, 1986
[3] Chandrakasan A.P. Sheng S. Brodersen R.W.: "Low-power CMOS digital design" , IEEE Journal of Solid-State Circuits, Volume 27, Issue 4, April 1992 Page(s):473 – 484
[4] Verma N. Kwong J. Chandrakasan A.P.: "Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits" , IEEE Transactions on Electron Devices, Vol. 55, NO. 1, January 2008 Page(s):163 – 174
[5] Mahmood, Sohail Musa, and Yngvar Berg."Ultra-Low voltage and high speed NP Domino carry propagation chain", 2013 IEEE Faible Tension Consommation, 2013..
[6] K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment", In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.
[7] T. Shibata and T. Ohmi. " A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", In IEEE Transactions on Electron Devices, vol 39, 1992. [8] Yungvar Berg, Omid Mirmothahari "High Speed and Ultra Low Voltage CMOS NAND and NOR Domino gates " IJECEECE Volumn 6.No.8. 2012