Series-1 (Mar. - Apr. 2021)Mar. - Apr. 2021 Issue Statistics
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|Paper Type||:||Research Paper|
|Title||:||Design and Implementation of 8-bit Vedic-Wallace Multiplier|
|Authors||:||G. Vishnu Pavan Reddy || Dr. Gargi Khanna|
ABSTRACT: The processors used in the electronic devices spend more time on multiplication operation compared to other arithmetic operations like addition and subtraction. Generally, multiplying two numbers includes basic shift and add operations which are used in Array multipliers. To speed up the multiplication process Conventional Wallace Tree Multiplier (WTM) is used, which is pipelined process and uses carry save adders to decrease the delay. To further increase the speed of the WTM, higher order compressors like 3-2, 4-2, 5-2, 7-2 etc., are used. In this paper we are designing an 8-bit Wallace Multiplier which uses an optimized 4-2 compressor circuit to decrease the power and delay of the multiplier. The design and simulation of the multiplier circuit is done on Tanner EDA tool version 16.0
Key Words: WTM, Compressor, PPG, PPR, DSP's, HA, FA
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