Series-1 (May - Jun. 2022)May - Jun. 2022 Issue Statistics
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|Paper Type||:||Research Paper|
|Title||:||Carbon Nanotube FET based high performance NAND Gate using Cascade Voltage Switch Logic|
|Authors||:||Sakshi || Shaveta Bala|
ABSTRACT: This paper depicts the design of NAND gate for nanotechnology. The basic elements which are used in the sketch is Carbon Nanotubes instead of the conventional silicon-based units. The special properties of the carbon nanotubes such as high thermal conductivity & electrical conductivity, aspect ratio, very elastic, high flexibility, high tensile strength, low thermal expansion coefficient and highly flexible which means can be bent considerably without damage. In addition to these basic properties, the Carbon nanotubes give a special opportunity of scaling the circuit design to the nano regime. The logic gate which is designed with the help of CNFETs and CVSL proved to be such an achievement that can ahead used to make complex circuits. The circuit proposed of the logic gate in this paper is designed using the 32nanometre Stanford units CNFET technology and is compared with the conventional.........
Keywords— CNFET, CVSL, NAND Gate.
 "Carbon Nanotube Based VLSI Interconnects", Springer Briefs in Applied Sciences and Technology, pp. 17-37, 2015.
 Rajendra Prasad Somineni, Y Padma Sai, S Naga Leela, "Low leakage cntfet full adders", IEEE Proceedings of Global Conference on Communication Technologies, pp. 174-179, April 2015.
 Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj, "A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications", Internation Journal of Circuit Theory & Application, Vol. 47, Issue 9, pp. 1-13, April 2019.
 Trapti Sharma, Laxmi Kumre, "Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology", Circuits, Systems, and Signal Processing ,Springer Science+Business Media, LLC, part of Springer Nature 2019, Vol. 39, Issue 12, pp. 3265–3288, 20.
 S Archana Dr. B K Madhavi Dr I V Murlikrishna, "Study of CNTFET Based Pattern Recognition Circuits in Comparison With CMOS Technology", IEEE International Conference on Modeling of Systems Circuits and Devices(MOS - AK India 2019, pp. 92-96.
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|Paper Type||:||Research Paper|
|Title||:||Design of a Radiation-Hardened SRAM Cell using 16nm Technology Node|
|Authors||:||Rajat M || Ram Rathan K R || Ranjithkumar N || Ravi L Bellubbi || Jamuna S|
ABSTRACT: Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over.........
Keywords— DEU; Radiation Hardening; RHBD; SET; SEU; DEU; SRAM
. N. Chen, T. Wei, X. Wei and X. Chen, "A Radiation Hardened SRAM in 180-nm RHBD Technology," 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, 2013, pp. 159-162
. N. K. Z. Lwin, H. Sivaramakrishnan, K. -S. Chong, T. Lin, W. Shu and J. S. Chang, "Single-Event-Transient Resilient Memory for DSP in Space Applications," 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 2018, pp. 1-5
. Yuanyuan Han, Tongde Li, Xu Cheng "Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2962-2975, July 2021
. C. Naga Raghuram, B. Gupta and G. Kaushal, "Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 1, pp. 181-190, March 2020
. D. Patel and N. Gajjar, "An Investigation of Single Event Upset Hardened SRAM Bit Cells," 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2021, pp. 1-4.