iosr-JVSP   Volume-9 ~ Issue-1 ~ Jan-Feb 2019

ABSTRACT: The work consist of two phases. The first phase of the work aims at finding out the optimized value of the fraction used in fractional filtering for image enhancement techniques in digital image processing. The work is done on MATLAB platform. The work starts with a comparative study of fractional order filter and integer order kernel filters like Sobel and Prewitt filters, used for edge detection and boundary detection of various digital images. With the view of applying fractional filtering in medical images, the work is done by utilizing Magnetic Resonance Imaging (MRI). The noise performances of these filters are analyzed upon the addition of random Gaussian noise. The mean......

[1]. R.C. Gonzalez and R.E. Woods, Digital Image Processing, 2nd ed. Prentice Hall, 2002.
[2]. V. Torre and T.A. Poggio, On edge detection, IEEE Trans. Pattern Anal. MachineIntell., vol. PAMI-8, no.2, pp. 187-163, 1986.
[3]. K.B. Oldham and J. Spanier, The Fractional Calculus, Academic Press, New York, NY,USA, 1974.
[4]. Whalley LJ. Spatial distribution and secular trends in the epidemiology of Alzheimer'sdisease, Neuroimaging Clin. N. Am. 2012;22 (1): 1-10, vii.
[5]. Samar.M.Ismail, Ahmed G Radwan, Ahamed H Madian and Mohamed F, ComparativeStudy of Fractional Filters for Alzheimer Disease detection on MRI Images, IEEE, 39th International Conference on Telecommunication and Signal Processing, pp 720723, 2016...

ABSTRACT: The Viterbi algorithm is generally used in decoding convolutional codes utilized in communications. In this paper Viterbi decoder and convolution encoder is designed, used in speech to text conversion.We can utilize three variations for re-computing with operands and itsalterations. The modified full adder circuit is subjected to low power consumption and low area. This can be implemented in Application Specific Integrated circuit (ASIC). This paper explains reduction of power and area by utilization ofmodified full adder. In this,viterbi decoder is designed by utilizing the modified full adder. viterbi decoder and convolution encoder are implemented in speech to text conversion application.

Keywords: Looking forward the procedure, re-computing throughencrypted operands, trellis.

[1]. A.J. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm," IEEE Trans. Inf. Theory, vol. IT-13, no. 2,pp.260-269, Apr. 1967.
[2]. R. Liu and K. Parhi, "Low-latency low complexity architectures for viterbidecoders,"IEEE Trans. Circuits syst. I. Reg. papers, vol. 56, no. 10, pp.2315-2324, Oct. 2009.
[3]. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and implementation. Hoboken, NJ, USA: Wiley, 1999.
[4]. G. Fettweis and H. Meyr, "parallel Viterbi algorithm implementation: Braking the ACS-bottleneck," IEEE Trans. Commun., vol. 37, no.8, pp.785-790, Aug. 1989.
[5]. V. Gierenz, O. Weiss, T. Noll, I. Carew, Ashely, and R. Karabed, " A 550mb/s radix-4 bit-level pipelined 16-state 0.25um CMOS viterbi decoder", in proc. IEEE Int. Conf. Appl-specific Syst. Archit. Process. Jul. 2000, pp.195-201.

ABSTRACT: More than 50% of random logic power in an SOC chip is typically consumed by Flip Flop. This is because of redundant transition of internal nodes, when the input and output appear to be in the same state. Different low power techniques have been proposed, but all of these designs use more transistor,leading to an increase in size, which is too costly since flip flops typically account for 50% of random logic area. In this paper we design D flip-flop using 2x1 multiplexer which has reduced transistor count compared to other low power designs of D flip-flops. The focus is to design high speed, low power consumption, positive edge triggered conventional D flip-flop which can be..........

Keywords: D flip-flop, 12 Bit register, Cadence Tool, CMOS circuit, 2x1 Multiplexer

[1]. Massoud Pedram., 1995 Design Technologies for Low Power VLSI, Encyclopedia of Computer Science and Technology,
[2]. Gray Yeap and Gilbert, 1998 Practical Low power Digital VLSI Design, Kluwer Academic Publishers.
[3]. Rabaey.J, 2003 Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice-Hall.
[4]. Pedram, . 1996,Power Minimization in IC Design, ACM Transactions on Design Automation of Electronic Systems, Vol 1, No. 1, pp. 3-56
[5]. Jui-Ming Chang and Massoud Pedram. 1997,Energy Minimization Using Multiple Supply Voltages", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 4, Pp: 436-444,.

ABSTRACT: Epileptic seizure is neurological disorder which can be diagnosed by using Electroencephalography, in this paper online database is used which is preprocessed and artifact removal of EEG signal is carried out. The primary features and secondary features such as mean, standard deviation, variance, skewness, kurtosis are found, which are given for a linear classifier which is Support Vector Machine for classification as seizure or non-seizure. Performance analysis of algorithm is also carried out by calculation of sensitivity, specificity and accuracy.

Keywords: Artifact, Electroencephalogram, Independent Component Analysis, Kurtosis, Seizure, Support Vector Machine.

1]. Fisher RS, van Emde Boas W, Blume W, et al. Epileptic seizures and epilepsy: definitions proposed by the International League Against Epilepsy (ILAE) and the International Bureau for Epilepsy (IBE). Epilepsia. 2005; 46(4):470-472.
[2]. Mr. Sanjay Pawar, Dr. Mrs. S.R.Chougule, Mr. A.H.Tirmare, Diagnosis of Epilepsy a Neurological Disorder Using Electroencephalogram (EEG) International Journal of Modern Trends in Engineering and Research Volume 4 Issue 6,PP. 144-149.
[3]. CHB-MIT scalp EEG database [Online]. Available: http://physionet.org/physiobank/database/chbmit/
[4]. Sornmo L, Laguna P. Bioelectrical signal processing in cardiac and neurological applications, Elsevier Academic Press, 2005. ISBN: 0-12- 437552-9
[5]. Fisch, BJ. EEG PRIMER Basic principles of digital and analog EEG, 3rd edition, Elsevier Academic Press, 1999. ISBN: 0-444-82147-3

ABSTRACT: In recent VLSI technologies to design any circuit main prime factors are speed and power with downscaling of chip size.Shift registers are used for temporary storage of data in processors and sequential circuits. The paper enumerates an efficient design of shift register in terms of speed and power consumption using 180 nm technology.Serial In Serial Out (SISO) and Serial In Parallel Out (SIPO) shift register has been designed using BICMOS logic. These shift registers have implemented by master slave D flip flop as a storage element.Cadence EDA tool has used to implement the proposed shift registers. Proposed design results compared with conventional design results implemented using CMOS technologyand concluded that proposed design has low power consumption and high speed compared to conventional design.

Keywords: BICMOS, Master-Slave D flip flop,Latch up, Cadence, Shift Register..

[1]. Divya Bora, Dr. U. M. Gokhale, "Design of Different Devices using BICMOS Logic", International Journal of Latest Research in Engineering and Technology (IJLRET),(2016), vol. 2,issue 5, page 69-73.
[2]. Raj Kumar Mistri, Rahul Ranjan, Pooja Prasad, Anupriya"IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System International Journal of Engineering Research & Technology (IJERT), (2017), vol. 6,issue 4, page 252-256.
[3]. A.Lakshmi, Dr.P.Chandrasekhar Reddy, "Design and Simulation of Low Power, High Performance Registers using MUX Based D Flip-Flop", IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), (2019), vol. 9, issue 1 page 14-22.
[4]. Achyutpandey, Ravi Mohan, Vivek Dubey, "Design and analysis of self clocked flip-flop based shift registers using 90 nm CMOS technology", International Journal of scientific research and management (IJSRM), (2015), vol. 3, issue 3,page 2397-2400.
[5]. VikasFageria,Vipin Gupta, "Low power shift register using nand gate with 130nm cmos design", International Journal of Innovative Science and Research Technology,(2016), vol. 1,issue 3, page 7-13.

ABSTRACT: The Present research work, a new performance and area optimization algorithm for complex VLSI systems is presented. The floorplanning is employed to calculate to the relative location of blocks within the fixed outline. The planning obscurity is increasing and therefore the circuit size is obtaining additional. Thus ultimately area of the circuit gets rise and harder to optimize the Wirelength and area. By using the genetic algorithms in the performance and area optimization, we are able to find the optimal values for both delay and silicon area for the MCNC benchmark circuits. PSO is a recent intelligent heuristic search method in which the mechanism of algorithm is inspired by the swarming of biological populations. In fact, both of them use a combination of deterministic...........

Keywords: VLSI, genetic Algorithm, PSO, MCNC benchmark.

[1]. P.K. Tripathi, S. Bandyopadhyay, K.S. Pal, Multi-objective particle swarm optimization with time variant
inertia and acceleration coefficients, Information Sciences 177 (22) (2007) 5033–5049.
[2]. A.S. Mohais, R. Mohais, C. Ward, Earthquake classifying neural networks trained with dynamic neighborhood PSOs, in:
Proceedings of the 9th Annual Conference on Genetic and, Evolutionary Computation (GECCO‟07), pp. 110–117.
[3]. G.S. Tewolde, D.M. Hanna, R.E. Haskell, and Multi-swarm parallel PSO: hardware implementation, in: Proceedings of the 2009
IEEE Symposium on Swarm (2009).
[4]. D.H. Lehmer, Mathematical methods in large-scale computing units, Ann. Computing Lab. Harvard Univ. 141-146, 1951.

[5]. V.LeelaRani, M.Madhavi Latha, "Implementation of genetic algorithm for minimum leakage vector in input vector control approach", IEEE conference,SPACES,Jan2015

ABSTRACT: The added value in this work is the integration of MICS with its local and small range (2m) and high efficiency with proposed WBAN network thus achieving the highest resolution benefit from both technologies for a realizable WBAN system of low power usage & high bit rate & low range , and wide coverage. Building embedded system that provides compact, secure, low-power, wireless, plug-and-play sensor networks that ensure safety for user by considering the standard international safety guidelines. The wireless sensor networks will collect patient information remotely that leads our research into: 1-Integrating real-time patient data into patient records, 2-High assurance software to collect valid sensors measurement and interconnect sensors information network to patient records.........

[1]. Hafez Fouad, Hesham Farouk, " Design and Implementation of Wireless Sensors Network and Cloud Based Telemedicine System for Rural Clinics and Health Centers", International Journal of Scientific & Engineering Research (IJSER), Vol. 6, Issue 2, February 2015
[2]. Hafez Fouad, ― Implementation of Remote Health Monitoring in Medical Rural Clinics for Web Telemedicine System", International Journal of Advanced Networking and Applications (IJANA), Vol. 6 Issue 3, Nov-Dec 2014.
[3]. Hafez Fouad, ― Continuous Health-monitoring for early Detection of Patient by Web Telemedicine System ―, International Conference on Circuits, Systems and Signal Processing , Saint Petersburg State Politechnical University, Russia, Sep,23-25, 2014. ISBN: 978-1-61804-249-1.
[4]. Hafez Fouad, ― Patient-oriented Web Telemedicine system For Health Monitoring ", Journal of Communication and Computer, CA 91745, USA,Vol.11, Issue 2, pp-168-178, Feb., 2014.
[5]. J. G Webster,―Medical Instrumentation Application and Design‖,3rd edition, John Wiley & Sons,1999