iosr-JVSP   Volume-13 ~ Issue-6 ~ Nov - Dec. 2023

ABSTRACT: This paper presents the design and analysis of a 1-bit Arithmetic Logic Unit (ALU) with and without a full adder circuit. The objective of the study is to compare the outputs of the two designs considering the performance factors of delay, power, and surface area. The designs were implemented using Cadence Virtuoso and simulated using a 90 nm CMOS process technology. As such, the circuit is built from two paired MOS transistors (i.e., using both N- and P-type MOSs in the pull-down and pull-up circuits, respectively) having a 90 nm gate length. The gate widths are selected as 1 and 2 m, respectively......

Keywords: CMOS; ALU; Logic Gate; Adder; Performance Analysis; Cadence; 90 nm Node; VLSI.

[1]. M. H.Bhuyan, "History And Evolution Of Cmos Technology And Its Application In Semiconductor Industry," Southeast University Journal Of Science And Engineering (Seujse), Issn: 1999-1630, Vol. 11, No. 1, June 2017, Pp. 28-42.
[2]. M. H. Bhuyan, "Rf Semiconductor Devices Technology: History And Evolution, Prospects And Opportunities, Current And The Future," Southeast University Journal Of Science And Engineering (Seujse), Issn: 1999-1630, Vol. 12, No. 2, December 2018, Pp. 28-39.
[3]. M. H. Bhuyan, "Analytical Modeling Of The Pocket Implanted Nano Scale N-Mosfets," Phd Thesis, Eee Department, Buet, Dhaka, Bangladesh, 2011.

ABSTRACT: The Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) protocols are widely used for communication between microcontrollers, sensors, and other digital devices. The correctness and reliability of these protocols are essential for proper system functioning. Therefore, it is necessary to verify these protocols thoroughly to ensure that they are error-free. In this paper, a novel verification environment is proposed for the verification of SPI and I2C protocols using SystemVerilog. Since, SystemVerilog incorporates......

Keywords: Code coverage; functional coverage; SPI; I2C; System Verilog;.

[1]. Chetan N, and R. Krishna, "Verification of SPI protocol Single Master Multiple Slaves using System verilog and Universal Verification Methodology (UVM)", International Journal of Engineering Research and Applications, Vol. 11, Issue 7, July 2021.
[2]. Ananthula Srinivas, M.Kiran Kumar, and Jugal Kishore Bhandari., Design and Verification of Serial Peripheral Interface", International Journal of Engineering development and Research, Vol. 1, Issue 3, Dec. 2014, pp. 130 -136.
[3]. System Verilog Tutorial: https://www.chipverify.com/systemverilog/systemverilog tutorial[4]. F.Leens, "An Introduction to I2C and SPI Protocols," IEEE Instrumentation & Measurement Magazine, pp. 8-13, February 2009, DOI: 10.1109/MIM.2009.4762946
[5]. M.Sukhanya, and K.Gavaskar, "Functional Verification Environment for I2C Master Controller using System Verilog", 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN - 2017), March 16 – 18, 2017, Chennai, INDIA, DOI: 10.1109/ICSCN.2017.8085732.

ABSTRACT: With the comprehensive advance of the new curriculum reform, how to promote the effective application of mathematics culture in teaching has become a topic of wide concern to educators. This paper firstly summarizes the connotation and value of mathematics culture, then discusses the current situation of the application of mathematics culture in high school mathematics teaching, and finally puts forward the application strategy. It includes improving teachers' professional quality, build ing the atmosphere o f mathematics culture and strengthening the connection with other subject s..

Keywords: Mathematical Culture; High School Mathematics Teaching; Application Strategy

[1]. Shi Mingkui.Stimulating Learning Interest and Carrying Forward Mathematics Culture The Infiltration of Mathematics Culture in High School Ma thematics Classroom Teaching [J]. Mathematics Learning and Research,2018(21):92.
[2]. L I Yannan. On the Application of Mathematics Culture in High School Mathematics Teaching [J]. Prose Hundred (New Chinese Binder),2019(06):91.
[3]. GE Yong. Effective Penetration an d Implementation Strategies of Mathematics Culture in High School Mathematics Teaching [J]. Mathematical Physical and Chemical Problem Research ,2022(36):11 13.
[4]. Zhao Guohua. On the Application of Mathematical Culture in High School Mathematics[J]. Huaxia Teachers,2020(14):68.

ABSTRACT: The need for high capacity long haul telecommunication system to carry huge traffic demands in recent times has lead to the use of optic fiber communication system because of its high capacity carrying advantage over wireless systems. But optic fiber signals suffer some signal impairment issues such as nonlinearity which tends to degrade its transmission performance. This paper proposed the use of adaptive optical equalizer to mitigate such impairments. To achieve that, a simulink model of the system was first developed for simulation experiments. Then the impact of out-of-bound nonlinear signal on the three key performance indicators (Q Factor, Bit Error.....

Keywords: Nonlinear optic fiber, self-phase modulation, Kerr effect, refractive index, nonlinearity mitigation

[1]. Paul E. and Green, Jr, 2003 " Fiber Optic Networks", Prince Hall, Englewood Cliffs, New Jersey,
[2]. Agrawal, G. P.,2001, "Nonlinear Fiber Optics", 3rd edition, Academic Press, San Diego, CA, 2001.
[3]. Poggiolini, P.; Jiang, Y. "Recent Advances in the Modeling of the Impact of Nonlinear Fiber Propagation Effects on Uncompensated Coherent Transmission Systems". J. Lightw. Technol. 2017, 35, 458–480. [CrossRef]
[4]. Golani, O.; Feder, M.; Shtaif, M. Kalman, "MLSE equalization of nonlinear noise". In Proceedings of the 2017 Optical Fiber Communications Conference and Exhibition (OFC), Los Angeles, CA, USA, 19–23 March 2017; Optical Society of America: Washington, DC, USA, 2017.
[5]. Golani, O.; Elson, D.; Lavery, D.; Galdino, L.; Killey, R.; Bayvel, P.; Shtaif, M. "Experimental characterization of nonlinear interference noise as a process of intersymbol Interference". Opt. Lett. 2018, 43, 1123–1126.

ABSTRACT: The Key Objective is HDL RTL Design Architecture of Ultra high multi Clock Frequency Speed Rate ( MHz, GHz, THz, PHz, EHz, ZHz, etc) Bits Per Second Baud Rate ) P.R.B.S(Pseudo Random Binary Sequence) Transceiver Soft A.S.I.C IP Core product for identification of the property of Different Pseudo Random Binary Sequence Patterns (Seed Words) of 2e7-1, 2e10-1, 2e15-1, 2e23-1, 2e31-1 tapped elements as per C.C.I.T.T-I.T.U Standards and IEEE-754 Single and Double Data Rate Data Precision Standards (32 bit & 64 Bit Data Width ) suited for Very Advanced Futuristic Hi-tech Smart High Speed Long Distance Wireless Digital Communication A.S......

Keywords: P.R.B.S- Pseudo Random Binary Sequence, Wi-Fi-Wireless Fidelity, F.P.G.A – Field Programmable Gate Array, IDE – Integrated Development Environment. C.C.I.T.T- Consulting Committee for International Telegraph and Telephone, I.T.U- International Telecommunication Union, A.S.I.C- Application Specific Integrated Circuit, E.D.A- Electronic Design Automation

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