| Paper Type |
: |
Research Paper |
| Title |
: |
Hardware Implementation of Face Detection Using ADABOOST Algorithm |
| Country |
: |
India |
| Authors |
: |
Ms.Vijayalami, Mr.B.Obulesu |
 |
: |
10.9790/2834-0124655  |
ABSTRACT: One of the main challenges of computer vision is efficiently detecting and classifying objects in an image or video sequence. Several machine learning approaches have been applied to this problem, demonstrating significant improvements in detection accuracy and speed. However, most approaches have limited object detection to a single class of objects, such as faces or pedestrians. A common benchmark for computer vision researchers is face detection. Given a set of images, a face detection algorithm determines which images have sub-windows containing faces. This task is trivial for humans, but is computationally expensive for machines. Most face detection systems simplify the face detection problem by constraining the problem to frontal views of non-rotated faces. Approaches have been demonstrated capable of relaxing these constraints, at the cost of additional computation. They utilize AdaBoost to select a set of features and train a classifier. The detector uses a cascade structure to reduce the number of features considered for each sub-window. This approach is significantly faster than previous techniques and is applicable for real-time systems. There is a need for hardware architectures capable of detecting several objects in large image frames, and which can be used under several object detection scenarios. In this work, we present a generic, flexible parallel architecture, which is suitable for all ranges of object detection applications and image sizes. The architecture implements the AdaBoost-based detection algorithm, which is considered one of the most efficient object detection algorithms
Keywords-AdaBoost, Correlator, Face Detection, FPGA,Template.
[1] J. MacQueen, "Some methods for classification and analysis of multivariate observations," in Proc. 5th Berkeley Symp. Math. Stat. Probab.,1967, pp. 281–297.
[2] K. Krishna, K. R. Ramakrishnan, and M. A. L. Thathachar, "Vector quantization using genetic K-means algorithm for image compression," in Proc. Int. Conf. Inf., Commun. Signal Process., Sep. 1997, pp. 1585–1587.
[3] Y.-C. Hu and M.-G.Lee, "K-means-based color palette design scheme with the use of stable flags," J. Electron.Imag., vol. 16, no. 3, pp. 033003 1–11, 2007.
[4] S. Ray and R. H. Turi, "Determination of number of clusters in K-means clustering and application in colour image segmentation," in Proc. 4th Int. Conf. Adv. Pattern Recog. Digit.Techn., 1999, pp. 137–143.
[5] M. Leeser, J. Theiler,M. Estlick, and J. J. Szymanski, "Design tradeoffs in a hardware implementation of the K-means clustering algorithm," in Proc. IEEE Sensor Array Multichannel Signal Process. Workshop, 2000, pp. 520–524.
[6] M. Estlick, M. Leeser, J. Theiler, and J. J. Szymanski, "Algorithmic transformations in the implementation of K-means clustering on reconfigurable hardware," in Proc. ACM/SIGDA Int. Symp. Field Program.Gate Arrays, 2001, pp. 103–110.
[7] A. G. d. S. Filho, A. C. Frery, C. C. de Araújo, H. Alice, J. Cerqueira, J. A. Loureiro, M. E. de Lima, M. d. G. S. Oliveira, and M. M. Horta, "Hyperspectral images clustering on reconfigurable hardware using the K-means algorithm," in Proc. Symp. Integr.Circuits Syst. Des., Sep. 2003, pp. 99–104.
[8] B. Maliatski and O. Yadid-Pecht, "Hardware-driven adaptive K-meansclustering for real-time video imaging," IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 1, pp. 164–166, Jan. 2005.
[9] T. Maruyama, "Real-time K-means clustering for color images on reconfigurable hardware," in Proc. Int. Conf. Pattern Recog., 2006, pp. 816–819.
[10] T.-W. Chen, C.-H.Sun, J.-Y.Bai, H.-R.Chen, and S.-Y. Chien, "Architectural analyses of K-means silicon intellectual property for image segmentation," in Proc. IEEE Int. Symp.Circuits Syst., May 2008, pp.2578–2581.
