iosr-JECE   Volume-4 ~ Issue-1

Abstract: The purpose of my project is to design & simulate the frequency divider using ADS software. My project is totally emphasized on the IEEE 802.11 a standard. The IEEE 802.11a describes the WLAN standard. The basis of the project is the SCL (Source Coupled Logic). This thesis organization provides an overview of the evolution of digitally programmable FREQUENCY DIVIDER using CMOS technology.
Keywords:Dual Modulus Prescaler, OFDM, RS Latch, SCL, Swallow Counter.

[1] Christopher Lam and Behzad Razavi, Member, IEEE " 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-m CMOS Technology".
[2] Masoud Zargari, Member, IEEE, David K. Su, Member, IEEE, C. Patrick Yue, Member, IEEE, "A 5-GHz CMOS Transceiver for
IEEE 802.11a Wireless LAN Systems ".
[3] Alexandre Marsolaist, Mourad N. El-Gamal1, and Mohamad Sawan"Department of Electrical & Computer Engineering, McGill
University, Canada "A CMOS. Frequency Synthesizer Covering the Lower and Upper Bands of 5GHz WLANs".
[4] B. Razavi, "Design considerations for direct-conversion receivers," IEEE Trans. Circuits Syst. II, vol. 44, pp. 428–435, June 1997.
[5] I. Bouras et al., "A Digitally Calibrated 5.15-5.825GHz Transceiver for 802.11a Wireless LANs in 0.18μm CMOS".
[6] P. Zhang et al., "A Direct Conversion CMOS Transceiver for IEEE 802.11a WLANs,"

Abstract:Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or low-area techniques developed specifically for digital filters can be found in. Many applications in digital communication (channel equalization, frequency channelization), speech processing (adaptive noise cancelation), seismic signal processing (noise elimination), and several other areas of signal processing require large order FIR filters ,since the number of multiply-accumulate (MAC) operations required per filter output increases linearly with the filter order, real-time implementation of these filters of large orders is a challenging task. This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitches is also reduced. This paper is implemented using XILINX ISE and hardware used is Spartan-3E and family is XC2S200E.
Keywords: Digital Filters, DSP, FIR, FPGA, Multipliers.

[1] Huang, Z. and M.D. Ercegovac, 2002. Signal gating for low-power array multiplier design. In: IEEE International Symposium on
Circuits and Systems, ISCAS‟2002, IEEE Computer Society, Washington DC., USA, pp: 489 -492. Doi:
10.1109/ISCAS.2002.1009884.
[2] Manish Bhardwaj, R. Min and A.P. Chandrakasan, 2001. Quantifying and enhancing power awareness of VLSI systems. IEEE
Trans. VLSI Syst.,9: 757-772.
[3] Meier, P.C.H., R.A. Rutenber and L.R. Carley,1999. Inverse polarity techniques for highspeed/low-power multipliers. In:
International Symposium on Low Power Electronics and Design, ISLPEAD‟1999, IEEE Computer Society,Washington DC., USA,
pp: 264-266.
[4] Kim, S. and M.C. Papaefthymiou, 2000.Reconfigurable low energy multiplier formultimedia system design. In: Proceedings of
IEEEComputer Society Workshop on VLSI, 2000, IEEEComputer Society, Washington DC., USA,pp: 129-134. Doi:
10.1109/IWV.2000.844541.
[5] Sinha, A., A. Wang and A. Chandrakasan, 2002. Energy scalable system design. IEEE Trans. VLSI Syst., 10: 135-145.
[6] Di, J., J.S. Yuan and R.F. DeMara, 2006.Improving power-awareness of pipelined array multipliers using 2-dimensional pipeline
gating and its application to FIR design. Integration the VLSI Journal.,39(2):9 112.doi:10.1016/j.vlsi.2004.08.2
[7] Di, J. and J.S. Yuan, 2003. Power-aware pipelined multipliers design based on 2-dimensional pipeline gating, Proceedings of 13th
ACM Great Lakes Symposium on VLSI 2003,Washington, DC, USA, 64-67.
[8] Hoang, Q.D., B.R. Zeydel and V.G. Oklobdzija, 2006. Energy optimization of pipelined digital systems using circuit sizing and
supply scaling. IEEE Trans. VLSI Syst., 14: 122-134.
[9] Lee, K.H. and C.S. Rim, 2000. A hardware reduced multiplier for low power design. In: Proceedings of the 2nd IEEE Asia-Pacific
Conference on ASICs, 2000, IEEE Computer Society, Washington DC., USA, pp: 331-334. Doi: 10.1109/APASIC.2000.896975.
[10] Parhi, K.K., 1999. VLSI Digital Signal Processing Systems. John Willey and Sons Inc., USA.

Abstract:Single hopping is implemented by using software approach over IEEE802.11WLAN card using orthogonality concept and protocol. Most feature of single hopping is to achieve virtual Wi-Fi network. Design parameters of this approach are time delay and energy consumption .There are many scenarios where a wireless device connect to virtual Wi-Fi network. In this paper we improve the energy consumption and reduce the switching delay over popular IEEE 802.11 WLAN and present the performance of virtual Wi-Fi for single hop ad hoc network in terms of delay and energy consumption. Finally we approached multihopping in an ad hoc network using channelization with node synchronization.
Keywords: Wi-Fi, ad hoc network, IEEE 802.11.

[1] Ranveer Chandra, Christ of Fetzer and Karin Hogstedt. Proceedings of Informatics, 1st International Conference on Ad-hoc
Networks and Wireless, Toronto, Vol. 16, pp 1-16, September 20-22, 2002. P. Barford and M. Crovella.
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Abstract:In today's high-tech environment, energy has become the impetus for socio-economic development. As a free, nonpolluting, inexhaustible, renewable energy, solar energy is ideal for generating electricity. Currently, generating electricity by solar energy is inefficient and costly. This paper is a result of prototype our main project which mainly focuses on how to improve its efficiency to develop an automatic solar tracking system which will keep the solar panels aligned with the Sun in order to maximize in harvesting solar power using ARM7 microcontroller. The system tracks the maximum intensity of light. When the intensity of light is decreasing, this system automatically moves too and fro to change its position and direction to get maximum intensity of light. LDR light detector is used to trace the coordinate of the Sun. While to rotate the appropriate position of the panel, a DC geared motor is used. And also tracking system can be moved in any position where ever there is sun rays' falling on the surface of building or ground. The relay driver is used to show how to conserve the electrical energy effectively when actually there is no need of electricity.
Keywords: four quadrant, photovoltaic cells, renewable energy, LDR sensors, ARM7 microcontroller

[1] Zhou Yan, Zhu Jiaxing "Application of Fuzzy Logic Control Approach in A Microcontroller-Based Sun Tracking System" 2010
WASE International Conference on Information Engineering.
[2] Chia-Yen Lee, Po-Cheng Chou, Che-Ming Chiang and Chiu-Feng Lin, "Sun Tracking Systems: A Review," Sensors, Sept.
2009, pp. 3875-3890, doi:10.3390/s90503875.
[3] Hj Mohd Yakup, M.A.; Malik, A.Q, "Optimum tilt angle and orientation for solar collector in Brunei Darussalam," Renew. Energ,
vol. 24, 2001, pp. 223-234.
[4] Bari, "Optimum slope angle and orientation of solar collectors for dfferent periods of possible utilization," Energy Convers.
Manage, vol. 41, 2000, pp. 855-860.
[5] McCluney, "Passive optical solar tracking system," Appl. Optics, vol. 22, 1983, pp. 3433-3439..
[6] Chen, Feng, Hong, "2006 Digital sun sensor based on the optical vernier measuring principle," Meas. Sci. Technol, vol. 17, 2006,
pp. 2494-2498
[7] Chong, K.K.; Wong, C.W, "General formula for on-axis sun tracking system and its application in improving tracking accuracy of
solar collector," Sol. Energ, vol. 83, 2009, pp. 298-305.
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Abstract:Cellular communication systems are the most widely used wireless communication systems. It is our primary need today to achieve the higher data rates in limited spectrum bandwidth to improve the performance of signals. We know digital communication system outperforms analog ones in terms of noise performance and flexibility. Hence, there has been great deal of search for a digital communication system that is bandwidth efficient and has low bit error rate at a relatively low signal to noise ratio. Various digital modulation schemes are incorporated but they are not feasible or cannot fulfil actual requirement varying in different kind of environment. In this paper we provide a general theoretical approach to analyze various M-ary modulation schemes using MATLAB taking BER as measure of performance when the system is subjected to AWGN and multipath Rayleigh fading channel. Based on these performances a desirable modulation scheme is suggested that provides low BER at low received SNR, performs well in multipath & fading conditions occupies a minimum of bandwidth and is easy & cost effective to implement in present cellular communication.
Keywords: Phase Shift Keying (PSK), Bit Error Rate (BER), Signal-to-Noise Ratio (SNR), AWGN (Additive White Gaussian Noise).

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Abstract:In this paper, Data link control in data communication is discussed. The control done by the Data link
layer is Data link control. It mainly does three controls that are its functions and their advantages.

[1] A.Harish Babu, P.Ashesh Babu, E.Vamsi Krishna IETE Members and Research students in kl-university.
[2] C. Balanis, Antenna Theory, Analysis and Design, 3rd edition, New York: Wiley, 2005. 2.
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Abstract:Dual reflector antennas are considered as pencil beam antennas that can produce radiation identical to searchlight. Cassegrain Reflector Antenna Design consists of various effects caused by blockage by primary feed or by the subreflector and its effect on overall performance. The objective of the paper is to provide the overview of the designing approach that is used to design the axially symmetric cassegrain antenna. This paper also provides the reader the overview of the various challenges and limitation that are faced by the designer while designing the axially symmetric dual reflector cassegrain system..
Keywords: Cassegrain Antenna, dual reflector design, minimum blockage condition, feed system.

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