iosr-JECE   Volume-4 ~ Issue-2

Abstract: ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 specifications which includes Advanced eXtensiable Interface (AXI) 4.0. AMBA bus protocol has become the de facto standard SoC bus. That means more and more existing IPs must be able to communicate with AMBA4.0 bus. Based on AMBA 4.0 bus, we designed an Intellectual Property (IP) core of Advanced Peripheral Bus (APB) Bridge, which translates the AXI4.0-lite transactions into APB 4.0 transactions. The bridge provides an interfaces between the high-performance AXI bus and low-power APB domain.
Keywords:SoC, AMBA, AXI, APB

[1] Design and Implementation of APB Bridge based on AMBA 4.0 (IEEE 2011), ARM Limited.
[2] http://en.wikipedia.org/wiki/System_on_a_chip#Structure
[3] Power.org Embedded Bus Architecture Report Presented by the Bus Architecture TSC Version 1.0 – 11 April 2008
[4] http://www.arm.com/products/system-ip/amba/amba-open-specifications.php
[5] ARM, "AMBA Protocol Specification 4.0", www.arm.com, 2010 ARM,AMBA Specification (Rev 2.0).AMBA® 4
AXI4™, AXI4-Lite™, and AXI4-Stream™ Protocol Assertions Revision: r0p0 User Guide.
[6] AMBA® APB Protocol Version: 2.0 Specifications.
[7] ASB Example AMBA System Technical Reference Manual Copyright © 1998-1999 ARM Limited.
[8] AHB to APB Bridge (AHB2APB) Technical Data Sheet Part Number: T-CS-PR-0005-100 Document Number: IIPA01-
0106-USR Rev 05 March 2007.
[9] LogiCORE IP AXI to APB Bridge (v1.00a) DS788 June 22, 2011 Product Specification.
[10] Simulation and Synthesis Techniques for Asynchronous FIFO Design Clifford E.Cummings, Sunburst Design, Inc.
SNUG San Jose 2002 Rev 1.2., FIFO Architecture, Functions, and Applications SCAA042A November 1999.

Abstract:This article presents the design of L-band branch line balun using microstrip configuration on high resistive silicon substrate (ρ>8KΩ-cm). In comparison to earlier designs better performance is achieved by meandering all the four branches and appending a quarter wavelength short circuited stub at the upper right corner of the structure. The circuit is designed using circuit simulator of Agilent's advanced design system (ADS) and further verified using Ansoft's FEM and ADS's MoM based electromagnetic solvers. Comparative study is carried out among various simulation techniques and analyzed. Fabrication methodology along with design steps are detailed in this article. Proposed design saves around 60% print area as compared to conventional topology. Further comparison with other reported topologies have also been discussed.
Keywords: Branch line balun, high resistive silicon, microstrip line, short circuited stub, via hole.

[1] Microwave Engineering-D.M Pozar, Wiley & Sons, Student Edition 2010.
[2] Ghali, H. and T. A. Moselhy, "Miniaturized fractal rat-race, branch-line, and coupled-line hybrids," IEEE Trans. Microwave Theory
Tech., Vol. 52, 2513-2520, 2000.
[3] Ang, K. S., Y. C. Leong, and C. H. Lee, "Multisection Impedance-transforming coupled-line baluns," IEEE Trans. Microwave
Theory Tech., Vol. 51,536-541, 2003.
[4] Zhang, Z. and S. Xu, "A novel balun structure with a composite right left-handed transmission line," Microwave Opt. Technol. Lett., Vol. 45, 422-424, 2005.
[5] RF and Microwave Coupled Line Circuits-Mongia, Bahl, Bhatia and Hong, Artech House, 2010.
[6] Tseng C.F and Lu S.C "A Broadband Balun using meander line" Progress in Electromagnetic Research Symposium, Suzhou,
China. ISSN 1559-9450, 501-504 September 12-16, 2011.
[7] Kamaljeet Singh, Ayan Karmakar & K. Nagachenchaiah," Dual Band(1:4) Wilkinson Power Divider on Silicon", International
Journal of Electronics ,Vol.1, No.1,pp.4-6, May 2012.
[8] Kamaljeet Singh, Ayan Karmakar & K. Nagachenchaiah,"Design and Development of X-band Planar Balun on Si substrate",
submitted for Journal Publication, "unpublished".
[9] Li, J. L., S. W. Qu, and Q. Xue, "Miniaturized branch-line balun with bandwidth enhancement," IEE Electron. Lett. Vol. 43, pp
931-932, 2007.
[10] ADS 2009, Agilent Technologies.

Abstract:Mining frequent itemsets is one of the most investigated fields in data mining. It is a fundamental and crucial task. In data mining approach, the quantitative attributes should be appropriately dealt with as well as the Boolean attributes. Apriori Algorithm is one the best methods to extract the frequent mining Data Set. This paper gives us a brief review of apriori algorithm along with its uses to various fields and with various algorithms.
Keywords: Association rules, Apriori algorithm, Data mining, frequent itemsets.

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[4] Algorithm Based on Redundacy of Rules", IEEE, pp. 68 -73, 2010.
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Proceedings of the ACM SIGMOD International Conference on Management of Data, Tuscon, Arizona, pp. 265-276, 1997.
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Abstract:Abstract:"Beginning with practical difficulties in teaching communication systems in class room, this paper describes a set of innovative experimental demonstrations developed using SDR". Communication engineering is one of the interesting, at the same time difficult subject to learn if the concept is not clear or well explained. Normal practice is that the faculties will just give a theoretical class on communication systems and for students the various communication processes like filtering, modulation, demodulation etc. are just imaginary things. Giving a clear idea about these things to a graduate and under graduate student is a little difficult task. The main aim of SDR is to create an attractive learning platform for the students where they are freed from the boring routine of theoretical learning. We are challenging current education system to think outside the "board", where students will feel excited to learn something new so that they can physically feel and have a real time experience, which would be quite difficult to forget, for which the expense required would be quite high. So in order to better our possibilities, we suggest this software which would equip them to visualize a solid image of what they are learning about. Another fact is that as this software is so simple and is easy to learn and is feasible for everyone who would like to have basics in electronics and communication. This software is worth a stepping stone for those who would dream about being a "real" engineer. This will boost engineering students having great struggle to understand and learn communication subjects. The soul of education system should transform from "cramming as you learn" to "see as you learn'.
Keywords:Attractive learning platform, GNU Radio, SDR, USRP, Experimental demonstration.

[1] Sharlene Katz"Using Software Defined Radio (SDR) To Demonstrate Concepts In Communications and Signal Processing
Courses", Proceedings of the 39th ASEE/IEEE Frontiers in Education Conference, 2009.
[2] "Goodman, Peter "A Software-Defined Radio Project for First Year ECET Students", Proceedings of the ASEE Annual
onference, 2007.
[3] Kubichek, Robert, et al, "A Comprehensive Suite of Tools for Teaching Communications Courses", Proceedings of the ASEE
Annual Conference, 2006.
[4] Dunne, Bruce, and Cooke, Melvin, "Design of a Hardware Platform foe analog Communications Laboratory", Proceedings of
the ASEE Annual Conference, 2008.
[5] Frolik, Jeff, "Laboratory Enhancement of Digital and Wireless Communications Courses", Proceedings of the ASEE Annual
Conference, 2005.
[6] Reed, Jeffrey, "Software Radio: A Modern Approach to Radio Engineering", Prentice Hall, 2005.
[7] Bard, John and Kovarik, Vincent, "Software Defined Radio: The Software Communications Architecture, "Wiley series in
software radio, 2007.
[8] Ramanathan R, "Implimentation of a Low Cost Synthetic Aperture Radar using software defined radio", Proceedings of second
international Conference on computing. Communication and networking technologies, 2010.
[9] Ettus Research LLC:http://www.ettus.com
[10] Soft rock and other SDR Radios:http://www.softrockradio.org/

Abstract:Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested using DSCH tool. Power analysis is carried out using MICROWIND tool.
Keywords: Low Power, Power gating technique, Sleep mode, FPGA

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IEEE/ACM International Symposium on Micro architecture, 2000. pp. 191-201.
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MASAUM Journal of Reviews and Surveys,Vol. 1, No.1, 2009.
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[5] Neil H.E.,David Harris, "CMOS VLSI Design" Third Edition, Boston: Pearson, 2005 .
[6] Anantha P. Chandrakasan and Robert W. Brodersen "Minimizing Power Consumption in CMOS Circuits" Department of EECS,
University of California at Berkeley.
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IEEE, April 1995, pp. 595-606.
[8] Power Optimization [Online]. Available: http://en.wikipedia.org/wiki/Power_optimization_(EDA).
[9] Power optimizations in FPGA designs [online]. http://www.altera.com/literature/cp/cp-pwropt.pdf.

Abstract:Portable multimedia and digital signal processing (DSP) systems, which typically require flexible processing ability, low power consumption, and short design cycle, have become increasingly popular over the past few years. Many multimedia and DSP applications are highly multiplication intensive so that the performance and power consumption of these systems are dominated by multipliers. The computation of the multipliers manipulates two input data to generate many partial products for subsequent addition operations, which in the CMOS circuit design requires many switching activities. Thus, switching activity within the functional unit requires for majority of power consumption and also increases delay .this approach dynamically detects the input range of multipliers and disables the switching operation of non effective ranges .Therefore, minimizing the switching activities can effectively reduce power dissipation and increase the speed of operation without impacting the circuit's operational performance. Here attempt is made to combine configuration, partially guarded computation, and the truncation technique to design a high speed and powerefficient configurable BM (CBM). The main concerns are speed, power efficiency and structural flexibility. The proposed multiplier not only perform single 16-b, single 8-b, or twin parallel 8-b multiplication operations but also offer a flexible tradeoff between output accuracy and power consumption to achieve more power savings.
Keywords: Booth multiplier (BM), configurable booth multiplier (CBM).

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Abstract:This paper presents the design and fabrication of bandpass filter for frequency-modulated continuous wave radar system. A bandpass filter was designed at the operating center frequency of 456 MHz, bandwidth of 60 MHz, 3 dB insertion loss, 1.1 VSWR, 50 ohm impedance. The design filter was simulated using ADS 2011. The outcome of this research was a prototype of a 456 MHz bandpass filter and the results of the measurement were approximately similar to the required specifications.
Keywords:bpf, bandwidth, insertion loss, vswr

[1] Alaydrus, M, Designing Microstrip Bandpass Filter at 3.2 GHz, International Journal on Electrical Engineering and Informatics,
2(2), 2010, 71-78.
[2] White FJ, High Frequency Technique (New Jersey, John Wiley & Sons, 2004).
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30: 646-653.
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Abstract:The latest development of Broadband Power Line Communication Network may offer a platform for synchrophasor-sensor network in power distribution networks to establish a smart grid. Random data traffic passing through the slave-station of synchrophasor-sensor network can be viewed as packet entering of a queue. Since the length of queue is limited the packet loss may occur. This negatively affects the queuing system performance. Our numerical evaluation shows that for 1,000 random packet arrival, with 14-150 Mbps arrival rate, 100 Mbps service rate, and 64 Mbit buffer capacities, there is average packet loss of 6.75 %. If the buffer capacity is increased to 128 Mbit, then average of packet loss is reduced to 6.69 %. Our numerical test shows that the option to increase queue service rate may reduce packet loss probability more significantly than to increase the buffer capacity of the queue system.
Keywords:Broadband PLC; Network; Packet loss; Queue

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