ABSTRACT: With ever increasing IC complexity and aggressive technology scaling towards cutting edge technologies, the SOC timing closure is becoming a tedious, time consuming and challenging task. Also in advanced technology nodes one has to consider the effect of PVT variation, temperature inversion, noise effect on delay, which is adding more scenarios for STA to cover. In this work, we have proposed an algorithm for simultaneous usage of data path ECO and clock path ECO for efficient timing closure in SOC. The algorithm here tries to fix multiple failing end points through simple clock path optimization, instead of performing data path optimization across multiple paths, thus reducing area and power overhead............
Keywords: Engineering Change Order ECO, Clock rescheduling / Clock push pull, physically aware, Distributed Multi Scenario Analysis
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