iosr-JVSP   Volume-2 ~ Issue-2

ABSTRACT: Nowadays Embedded Systems have became a part of human life. The most important part of an embedded system is the embedded processor. The performance of embedded processor determines the performance of embedded system. An embedded processor is a Reduced Instruction Set Computer (RISC). In this paper the procedure for designing, implementing and testing a 16 bit RISC processor is presented. This processor was implemented in XC3S400 Field Programmable Gate Array (FPGA) and tested on XC3S400 FPGA development board. This processor is useful for demonstrating hazards in pipeline and the techniques used to solve them.

Keywords - Arithmetic and logical unit (ALU), Input output block (IOB), Integrated software environment (ISE), Look up table (LUT), Very high speed integrated circuit hardware descriptive language (VHDL)

[1] David A. Patterson and John L. Hennessy, Computer organization and design (Morgan Kaufmann, 1998)
[2] Douglas Perry, VHDL Programming (Tata McGraw Hill)
[3] John Wakerly, Digital design (PHI

ABSTRACT: In this paper, image smoothening, gradient magnitude, hystersis used in Canny edge detection algorithm is presented. The new algorithm used has a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the Canny edge detector. This also achieves less memory requirements, decreased latency and increased throughput with no loss in edge detection. Furthermore, the hardware architecture of the proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex 5 FPGA. The design development is done in VHDL and simulated results are obtained using modelsim 6.3 with Xilinx 12.2.

Keywords: - Canny Edge detector, Distributed Processing, FPGA, Non-uniform quantization.

[1] L. Torres, M. Robert, E. Bourennane, and M. Paindavoine, "Implementation of a recursive real time edge detector using Retiming techniques," VLSI, Aug. 1995, pp.811 –816.
[2] J. Canny, "A computational approach to edge detection,"IEEE Trans. PAMI, vol. 8, no. 6, Nov. 1986, pp. 679 –698.
[3] Qian Xu, Chaitali Chakrabarti and Lina J. Karam,"A Distributed Canny Edge Detector and Its Implementation On FPGA", Arizona State University, Tempe, AZ. 2011.
[4] S. Varadarajan, C. Chakrabarti, L. J. Karam, and J. M.Bauza, "A Distributed psycho-visually motivated canny edge detector," IEEE ICASSP, Mar. 2010, pp. 822 –825,.
[5] Željko Hocenski, Suzana Vasilić, "Improved Canny Edge Detector in Ceramic Tiles Defect Detection", Osijek, Croatia 6-10 Nov2006.
[6] W. He and K. Yuan, "An improved Canny edge detector and its Realization on FPGA," WCICA, Jun. 2008, pp. 6561 –6564.
[7] Anand Gupta , Ravi Kumar Dalal,Rahul Gupta,Pulkit Wadhwa "DOW-Canny: An Improvised Version Of Canny Edge Detector". (ISPACS) December 2011, pp. 7-9.

ABSTRACT:Image processing plays a major role in various applications. These images may be affected from noises that lead to disorder in embedding the messages. Inorder to overcome this problem various pre-processing techniques are involved. The main objective of this paper is to segment the image through watershed segmentation of image and can embed the secret messages. Extraction of segmentation is also done by adding the more morphological operations such as erosion, dilation, eroding, smoothing with an existing detectors such as sobel operators. This paper involves in evaluating the quality of an image with various techniques such as PSNR (Peak-Signal-to-Noise Ratio). Experimental results show that our proposed technique achieve good visual quality image with excellent PSNR values. This value provides high level security and more robust when compared to other combination of transformation technique.

Keywords: Stego image, Morphological operators, Edge segmentation, PSNR

[1] "Image Segmentation by Region based and Watershed Algorithms" Wiley Encyclopedia of Computer Science and Engineering, edited
by Benjamin Wah.Copyright # 2008 John Wiley & Sons, Inc
[2] IJCSI International Journal of Computer Science Issues, Vol. 7, Issue 5,September 2010 "A Study Of Image Segmentation Algorithms
For Different Types Of Images "Krishna Kant Singh, Akansha Singh21Deptt. Of Electronics & Communication Hermes Engineering
College Roorkee India2Deptt. Of Information Technology.
[3] International Journal of Computer Science & Information Technology (IJCSIT) Vol 3, No 5, Oct 2011 DOI : 10.5121/ijcsit.2011.3509
99 "RESEARCH REVIEW FOR DIGITAL IMAGE SEGMENTATION TECHNIQUES" Ashraf A. Aly1, Safaai Bin Deris2, Nazar
Zaki3 1, 2Faculty of Computer Science.
[4] IJCST Vol. 1, Iss ue 2, December 2010 "A New Proposed Method for Image Segmentation Based on Gray Scale Morphological
Transformations" 1Shahana Bano, 2M. Surendra Prasad Babu, 3C.Naga Raju Department of C.S.E, KLEF University, Guntur Distt,
Andhra Pradesh
[5] "Parallel Algorithm for Gray-scale Image Segmentation", Harvey A. Cohen, Proc, Australian and New Zealand Conf. Intelligent
Information Systems, ANZIIS-96, Adelaide, Nov 18-20, 1996, pp 143-146.
[6] "A New Proposed Method for Image Segmentation Based on Gray Scale Morphological Transformations" Shahana Bano, M. Surendr a
Prasad Babu, C.Naga Raju december 2010 IJCSt Vol. 1, Issues 2

ABSTRACT: In present days mixed signal design is very important in many of system applications like Analog to digital convertors, switching circuits and communication blocks. In ADC architecture comparator is the main functional block. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input is greater or smaller than applied references. Settling time is important in analog signal processing in order to avoid the errors in the accuracy of processing analog signal and to have fast settling time. To get the fast settling time the circuit must be with high slew rate. A longer settling time implies that the rate of processing analog signals must be reduced. In this paper presented design of CMOS comparator of high gain in order of 103 with slew rate of 10v/μs. This architecture is operates at 3V power supply and design is simulated using LT-SPICE tool. Transient response, ac analysis and slew rate results also shown and discussed in this paper.

[1] Razavi B., "Design of Analog CMOS Integrated Circuits", McGraw-Hill., Inc., Bosten, MA, 2001.

[2] H.P. Le, A. Zayegh and J. Singh , "Performance analysis of optimized CMOS comparator", IEEE E. Letters, Vol. 39, Issue 11, pp. 833 – 835,2003.

[3]. R. Gray and R. G. Meyer, "Analysis and Design of Analog Integrated Circuits," 3rd Edition, John Wiley & Sons, Inc., Hoboken, 1993.

[4] P. E. Allen and D. R. Holberg, "CMOS Analog Circuit Design," 2nd Edition, Oxford University, Oxford, 2007.

[5] A. Graupner, "A Methodology for Offset Simulation of Comparators," The Designer Guide Community, Oct. 2006.

ABSTRACT: In portable electronic devices that operate on battery power, it is essential to have power saving techniques to increase the operating time as they are energy constrained. This paper presents a novel power saving technique supported by two design models for multimedia purposes. The two designs are with two varying significance. The most significant part is turned off when it can't produce different results. This is done to save power consumption. The two design examples explored in this paper have varying hardware configurations thus reveal different realization. The models are namely multi-transform model and multimedia functional unit. The former computes three transforms for H.264 encoding while the latter supports six functions which are commonly used namely addition, multiplication, subtraction, interpolation, MAC and sum-of-absolute-difference. For these designs the proposed VLSI technique is capable of saving power by 27% and 24% respectively at the expence of 20% area overheads.

Index Terms - Low-power design, multimedia, digital signal processing, video coding, image coding

[1]. R. Schafer, T. Wiegand, and H. Schwarz, "The emerging H.264/AVC standard," EBU Technique Review Jan. 2003 [Online].
Available: http://www.ebu.ch/trev_293-schaefer.pdf
[2]. A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design"Circuits and Systems. Norwell, MA: Kluwer, 1995.
[3] K. Choi, R. Soma, and M. Pedram, "Dynamic voltage and frequency scaling based on workload decomposition," in Proc. IEEE Int.
Symp.Low Power Electron. Des., 2004, pp. 174–179.
[4] J. Choi, J. Jeon, and K. Choi, "Power minimization of functional units by partially guarded computation," in Proc. IEEE Int. Symp.
Low PowerElectron. Des., 2000, pp. 131–136.
[5] O. Chen, R. Sheen, and S. Wang, "A low-power adder operating on effective dynamic data ranges," IEEE Trans. Very Large Scale
Integr.(VLSI) Syst., vol. 10, no. 4, pp. 435–453, Aug. 2002.
[6] O. Chen, S.Wang, and Y. W.Wu, "Minimization of switching activities of partial products for designing low-power multipliers,"
IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, pp. 418–433, Jun. 2003.
[7] L. Benini, G. D. Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, "Glitch power minimization by selective gate freezing,"
IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 287–298, Jun. 2000.
[8] S. Henzler, G. Georgakos, J. Berthold, and D. Schmitt-Landsiedel, "Fast power-efficient circuit-block switch-off scheme," Electron.
Lett., vol. 40, no. 2, pp. 103–104, Jan. 2004.
[9] T. Xanthopoulos and A. P. Chandrakasan, "A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal
correlations and quantization," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 740–750, May 2000.

ABSTRACT: This paper compares the ratioed logic circuits and conventional CMOS design. This comparison performed on efficient CMOS circuit realizations and the ratioed logic circuits and it is resulted in to superiority of ratioed circuit over the conventional CMOS in some cases with respect to area, input capacitance. In this paper, 4-input NAND gate is designed using the conventional CMOS design and pseudo-NMOS logic design, which is the most common form of CMOS ratioed logic and the results are compared using Microwind and DSCH2 CMOS layout tools.

Keywords - CMOS, DSCH2 , PSEUDO-NMOS, NAND Gate , Microwind

[1]. "CMOS VLSI design" by Neil H.E. Weste, David Harris, Ayan Banerjee, page-221 to 222

[2]. Paul Kartschoke* and Norman RohreP*,IBM Microelectronics,IO00 River Rd. Essex Junction, VT 05452, USA

[3]. Christophe R. Tretz, Robert K. Montoye & William Reohr ,IBM T.J. Watson Research Center, Yorktown Heights, NY

[4] Microwind user manual and DSCH user manual. Retrieved February 2012 from Microwind commercial

[5] W.Wolf Modern VLSI Design-Systems on Silicon, Prentice Hall, 1998

[6] Introduction to VLSI Systems: A Logic, Circuit, and System Perspective by Ming-Bo Lin, page-350 to 352

ABSTRACT: Fast multipliers are essential components of most VLSI applications like digital signal processing systems, microprocessors, etc. The speed of multiplier operation is of fastidious importance within the general-purpose processors. The essential multiplication principle is twofold i.e., Evaluation of partial product and accumulation of the shifted partial products with the motivation to Booth's algorithm. In this pithy, an efficient design of modified Booth Encoder and Decoder scheme for high performance of parallel multiplier has been proposed. The proposed Booth encoder and Decoder logic are competitive with the present schemes and shows enhancements in delay. It additionally shows a substantial reduction in area.

Keywords - FPGA (Field Programmable Gate Array), Partial Product Generator (PPG), Radix-4 Modified Booth Encoder (MBE), Sign extension

[1] F. Lamberti, N. Andrikos, E. Antelo, and P. Montuschi, Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers, IEEE Trans. on Computers, vol. 60, no. 2, pp. 148-156, Feb. 2011.
[2] A. D. Booth, A Signed Binary Multiplication Technique, Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2, pp. 236–240, June 1951.
[3] 0. L. MacSorley, High-speed arithmetic in binary computers, Proc. IRE, Jan. 1961, vol. 49, pp. 67-91.
[4] G. Goto, et. al., A 4.1-ns Compact 54×54-b Multiplier Utilizing Sign-Select Booth Encoders, IEEE J. of Solid-State Circuits, vol. 32, no. 11, pp. 1676-1681, Nov. 1997.
[5] C.S.Wallace, A Suggestion for a Fast Multiplier, IEEE Trans. on Computers, vol. 13, no. 2, pp. 14-17, 1964.
[6] Ron S. Waters and Earl E. Swartzlander, A Reduced Complexity Wallace Multiplier Reduction, IEEE Trans. on Computers, vol. 59, no. 8, pp. 1134-1137, August 2010.
[7] J.-Y. Kang, W.-H. Lee, and T.-D. Han, A Design of a Multiplier Module Generator Using 4-2 Compressor, Proc. Korea Inst. Of Telematics and Electronics (KITE) Fall Conf., 1993, vol. 16, pp. 388-392.
[8] Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-seog Choi, 54x54-bit Radix-4 Multiplier based on Modified Booth Algorithm, ACM, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 2003, pp. 233-236.
[9] W.-C. Yeh and C.-W. Jen, High-Speed Booth Encoded Parallel Multiplier Design, IEEE Trans. on Computers, vol. 49, no. 7, pp. 692-701, July 2000.
[10] Kyung-Ju Cho, et. al., Design of Low-Error Fixed-Width Modified Booth Multiplier, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 522-530, May 2004.

ABSTRACT: Accurate brain tissue segmentation from magnetic resonance (MR) images is an essential step in quantitative brain image analysis. However, due to the existence of noise and intensity in-homogeneity in brain MR images, many segmentation algorithms suffer from limited accuracy. Here, we assume that the local image data within each voxel's neighborhood satisfy the Gaussian mixture model (GMM), and thus propose the fuzzy local GMM (FLGMM) algorithm for automated brain MR image segmentation with bias field correction. This algorithm estimates the segmentation result that maximizes the posterior probability by minimizing an objective energy function, in which a truncated Gaussian kernel function is used to impose the spatial constraint and fuzzy memberships are employed to balance the contribution of each GMM. Our results show that the proposed algorithm can largely overcome the difficulties raised by noise, low contrast, and bias field, and substantially improve the accuracy of brain MR image segmentation.

[1] U. Vovk, F. Pernus, and B. Likar, "A review of methods for correction of intensity inhomogeneity in MRI," IEEE Trans.Med. Imag., vol. 26, no. 3, pp. 405–421, Mar. 2007.

[2] W. Wells, E. Grimson, R. Kikinis, and F. Jolesz, "Adaptive segmentation of MRI data," IEEE Trans. Med. Imag., vol. 15, no. 4, pp. 429–442, Apr. 1996.

[3] V. Leemput, K. Maes, D. Vandermeulen, and P. Suetens, "Automated model-based bias field correction of MR images of the brain," IEEE Trans. Med. Imag., vol. 18, no. 10, pp. 885–896, Oct. 1999.

[4] Y. Zhang, M. Brady, and S. Smith, "Segmentation of brain MR images through a hidden Markov random field model and the expectationmaximization algorithm," IEEE Trans.Med. Imag., vol. 20, no. 1, pp. 45– 57, Jan. 2001.

[5] C. Li, C. Gatenby, L. Wang, and J. Gore, "A robust parametric method for bias field estimation and segmentation of MR images," in Proc. IEEE Conf. Comput. Vision Pattern Recog., 2009, pp. 218–223.

[6] C. Li, C. Xu, A. Anderson, and J. Gore, "MRI tissue classification and bias field estimation based on coherent local intensity clustering: A unified energy minimization framework," in Proc. 21st Int. Conf. Inf. Process. Med. Imag., Lecture Notes in Computer Science, 2009, vol. 5636, pp. 288–299.

[7] K. Sikka, N. Sinha, P. K. Singh, and A. K. Mishra, "A fully automated algorithm under modified FCM framework for improved brain MR image segmentation," Magn. Reson. Imag., vol. 27, pp. 994–1004, Jul.2009.

[8] D. Pham and J. Prince, "Adaptive fuzzy segmentation of magnetic resonance images," IEEE Trans.Med. Imag., vol. 18, no. 9, pp. 737–752, Sep.1999.

[9] M. Ahmed, S. Yamany, N. Mohamed, A. Farag, and T.Moriarty, "A modified fuzzy c-means algorithm for bias field estimation and segmentation of MRI data," IEEE Trans. Med. Imag., vol. 21, no. 3, pp. 193–199, Mar. 2002.

ABSTRACT: With the miniaturization of transistor size, fabrication of transistor with lithography technique is a foreseen problem. It is possible to routinely create semiconductor nanocrystals whose dimensions are much smaller than those can be realized by lithography techniques using colloidal chemistry. The size of the nanocrystals can be varied easily by varying the process parameters to study the quantum confinement effect. Here we present the simple synthesis method of Pb-CdSe and characterization of the same with XRD, UV-VIS spectroscopy and AFM. Also we present the I-V characteristics of Single Electron Transistor, by applying different values of Gate voltage. Decrease in the size of the nanoparticles will result in increase in charging energy and hence leads to more prominent Coulomb Blockade phenomena. Gate voltage controls the movement of electron from the blockade region and hence can be used in charge sensing application as they detect the motion of single electron.

Keywords: Single electron transistor, Lead Cadmium Selenide, Coulomb Blockade, IV characteristics, AFM

[1] A. Boubaker, N. Sghaier, M. Troudi, a. Kalboussi, N. Baboux, and a. Souifi, "A new SIMPLORER model for single-electron transistors," Microelectronics Journal, vol. 38, no. 8–9, pp. 894–899, Aug. 2007.

[2] D. L. Klein, R. Roth, A. K. L. Lim, A. P. Alivisatos, and P. L. Mceuen, "A single-electron transistor made from a cadmium selenide nanocrystal," no. October, pp. 5–7, 1997.

[3] P. Hadley, G. Lientschnig, and M. Lai, "Single-Electron Transistors," pp. 1–8.

[4] P. B. Agarwal and a. Kumar, "Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs)," Microelectronics Journal, vol. 42, no. 1, pp. 96–100, Jan. 2011.

[5] M.Kavosh Tehrani, A.R Gholamiyankhak, N.Tavakkoli, H.Tavallali,"Synthesis and Characterization of CdSe Nanoparticles by Chemical Route."World Applied Science Journal (Supplement 1) 41-44, 2009

[6] J. Zhu, X. Liao, X. Zhao, and J. Wang, "Photochemical synthesis and characterization of CdSe nanoparticles," no. February, pp. 339–343, 2001.

[7] K. Kandasamy, H. B. Singh, and S. K. Kulshreshtha, "Synthesis and characterization of CdS and CdSe nanoparticles prepared from novel intramolecularly stabilized single-source precursors," Journal of Chemical Sciences, vol. 121, no. 3, pp. 293–296, Jul. 2009.

[8] D. K. Dwivedi, V. Kumar, M. Dubey, and H. P. Pathak, "STRUCTURAL , ELECTRICAL AND OPTICAL INVESTIGATIONS OF CdSe NANOPARTICLES," vol. 1, no. 6, pp. 21–25, 2011.

ABSTRACT: This paper describes two different topology of voltage follower class-A voltage followers and class-AB voltage follower like flipped voltage follower and translinear voltage follower. Each follower has its own advantage and several limitations. The circuits are simulated in CMOS 0.18μm process technology. The two voltage follower characterized using ideal current source and then using a current mirror as a source current. The results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. Various topologies of voltage follower like Flipped voltage Follower and Translinear voltage follower are designed in 0.18μm technology with ±1.8V power supply. The analysis are made in terms of gain, bandwidth, offset and transient response using ELDO spice, IC station and Design architect of mentor graphics.

Keywords – Voltage Follower, Buffer, Flipped Voltage Follower, Translinear Voltage Follower.

[1] Yaohui Kong, Shuzheng Xu and Huazhong Y, "An Ultra Low Output Resistance and Wide Swing Voltage Follower", ICCCAS 2007, pp. 1007-1010, July 2007.
[2] Patt Boonyaporn and V. Kasemsuwan, "A High Performance Class AB CMOS Rail to Rail Voltage Follower", IEEE ASIA-Paci_c Conference on ASIC, pp. 161-163, 2002.
[3] Gaurang P. Banker, "Comparative Analysis of Low Power CMOS Class-A Voltage Followers with Current Mirror as a Load", IJECT Vol.2, Issue 2, pp. 108-111, 2011.
[4] Neeraj Yadav, "Low Voltage Analog Circuit Design Based on the Flipped Voltage Follower", IJECSE, vol. 1, no. 2, pp/ 258-273.ISSN.
[5] P. E. Allen and D. R. Holberg, CMOS Analog circuit design, Oxford University Press, 2nd ed., pp. 167-242, 2002.
[6] Franco Maloberti, Analog Design for CMOS VLSI Systems, Kluwer Academic/Plenum press,1998.
[7] Harry W. Li, R. Jacob Baker and David E. Boyce, CMOS Circuit Design, Layout and Simulation, IEEE Press Series on Microelectronics Systems, 2005.
[8] Stephen H. Lewls, Paul J. Hurst, Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, JOHN WlLEY and SONS, 4th ed., 2001.
[9] Neil H.E. Weste and David Harris, CMOS VLSI DESIGN: A Circuits and System Perspective, Pearson Education, 3rd ed., ISBN 0-321-26977-2, 2005.