iosr-JVSP   Volume-9 ~ Issue-6 ~ Nov. - Dec. 2019

ABSTRACT: This paper suggests a low power fixed-width multiplier using a reduced precision redundancy unit (RPR) for VLSI signal processing applications. RPR consists of a reduced precision module and a full precision module. The result of the reduced precision is considered as the correct output when the source output computes falsely. The proposed RPR fixed-width multiplier can satisfy the demand for accuracy, area efficiency, processing speed, and low power consumption. The precision of the proposed multiplier will be enhanced by the RPR logic. The compensation bias consists of probability and statistics. To avoid the truncation error many types of rounding methods are employed. The proposed RPR fixed-width multiplier is installed in the FIR filter design for various signal processing applications. The detailed analysis of the suggested multiplier gives 30% power reduction and 46.54% area reduction as compared with the different techniques.

Keywords- Fixed-width Multiplier; Reduced Precision Replica; Probability statistics; Error approximation; FIR filter

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ABSTRACT: In this paper, we define a family of simplex projection methods (SPM) for endmember selection. We give numerical results for two known endmember-selection procedures—the pixel purity index (PPI) and the
maximum distance (MaxD) methods. Then we compare these results to those for two examples of SPMs—the Farthest Pixel Selection (FPS) method and the Stepwise Simplex Projection (SSP) method. The numerical
examples using AVIRIS image data show that this new class of techniques gives better descriptions of the target and background regions than do current methods. This leads to more precise detection (with lower false alarm
rates) of low-visibility small (subpixel) targets.

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ABSTRACT: There are networks and entity groupings that require authentications while preserving the privacy of the entity being authenticated. Zero – Knowledge Proof (ZKP) plays a vital role in authentications without revealing secret information. Our proposed work carries criticism of ZKP, and Diffie–Hellman Key Exchange Algorithm (DHKEA). A new ZKP has been proposed based on modifications of the DHKEA. As per the modifications, two versions of the proposed protocols are developed. Verilog HDL is effectively utilized to complete the design of proposed protocols. Results will be verified through simulations and FPGA target board.

Key words: Authentication, Networks, Entity groupings Zero-Knowledge Proof, Verilog HDL, Simulations, FPGAs

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