iosr-JVSP   Volume-11 ~ Issue-1 ~ Jan. - Feb. 2021

ABSTRACT: For any kind of digital circuit, decreasing surface area is one of the crucial factors. Very Large Scale Integration (VLSI) technology is used to diminish the chip area to increase packing density as well as to increase performances. A full adder circuit is a digital circuit that is one of the important components in a computer or any kind of processor for arithmetic operation. Now 64-bit arithmetic operations are being performed. Therefore, we need a huge amount of area to perform this operation. Not only that, we need to reduce power consumption, noise margin.....

Key Word: CMOS; Full Adder; Technology Node; VLSI; Area; Power Consumption; Noise; Delay

[1]. S. Purohit and M. Margala, "Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance" IEEE Transaction Very Large Scale Integration (VLSI) Systems, Vol. 20, no.7, pp.1327-1331, July 2012.
[2]. B. R. Zeydel, D. Baran, V. G. Oklobdzija, "Energy -Efficient Design Methodologies: High-Performance VLSI Adders" IEEE Journal of solid-state circuits, Vol. 45, no. 6, pp.1220-1233, June 2010.
[3]. R. Yousuf and Najeeb-ud-din, "Synthesis of Carry Select Adder in 65 nm FPGA" IEEE Region 10 conference, pp.1-6, 2008.
[4]. A. M. Shams, T. W. Darwish, and M. A. Bayomui, "Performance analysis of low power 1 -bit CMOS full adder cells,‟ IEEE Transactions on Very Large Scale Integration (VLSI) Systems," Vol. 10, Issue 1, February 2002.
[5]. C. Senthilpari, S. Kavitha and J. Joseph, "Lower Delay and Area Efficient Non-Restoring Array Divider by Using Shannon Based Adder Technique," Proc. of ICSE 2010, Melaka, Malaysia, pp.140-144, 2010

ABSTRACT: A compact introduction to the use of Tanner's-EDA S-Edit and T-Spice tools is mandatory for students taking their first VLSI design course. The article present a few clear examples of design and simulation of basic building blocks in VLSI design. Their study will provide the student with the basic technical skills to move to more advanced design work.

Key Word: VLSI, CMOS, Tanner-EDA, Inverter, SPICE, Simulation, Circuit-design

[1] G. P. Patsis, Process-simulation-flow and metrology of VLSI layout fine-features, IOSR Journal of VLSI and Signal Processing, vol. 7, no. 6, 2017, 23-28.
[2] G. P. Patsis, VHDL-AMS macromodels of MOSFET. Consideration of gate length variability and single-electron-transistors, IOSR Journal of VLSI and Signal Processing , vol. 7, no. 6, 2017, 29-33
[3] G. P. Patsis, Basic topologies of MOS single-stage amplifiers. DC analysis for maximum input-voltage swing and amplification, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 1, 2018, 47-59.
[4] G. P. Patsis, MOSFET EKV Verilog-A model implementation in Genesys, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 2, 2018, 73-86.
[5] G. P. Patsis, Educational Introduction to VLSI Layout Design with Microwind, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 5, 2018, 18-29.

ABSTRACT: A simple version of the EKV MOSFET model is implemented in Verilog-A and tested with Tanner EDA software suite using S-Edit and T-Spice. The process of model development in Verilog-A and its integration into the software's library is discussed in detail. The aim of this work is to present the advantages of analog modeling with hardware description languages, especially when developing nonlinear device models, and to present the details of implementing a Verilog-A EKV MOSFET model in the simulator.

Key Word: EKV MOSFET, Verilog-A, S-Edit, T-Spice, Tanner-EDA.

[1] G. P. Patsis, MOSFET EKV Verilog-A Model Implementation in Genesys, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 1, 2018, pp. 73-86.
[2] G. P. Patsis, Process-simulation-flow and metrology of VLSI layout fine-features, IOSR Journal of VLSI and Signal Processing, vol. 7, no. 6, 2017, 23-28.
[3] G. P. Patsis, VHDL-AMS macromodels of MOSFET. Consideration of gate length variability and single-electron-transistors, IOSR Journal of VLSI and Signal Processing , vol. 7, no. 6, 2017, 29-33
[4] G. P. Patsis, Basic topologies of MOS single-stage amplifiers. DC analysis for maximum input-voltage swing and amplification, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 1, 2018, 47-59.
[5] G. P. Patsis, Educational Introduction to VLSI Layout Design with Microwind, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 5, 2018, 18-29.