iosr-JVSP   Volume-11 ~ Issue-5 ~ Sep. - Oct. 2021

ABSTRACT: In Very Large Scale Integration (VLSI) technology, the main objective is to shrink the area and thereby to raise the packing density for performance improvement in terms of power consumption, noise, delay, operating frequency, etc. A carry look-ahead adder circuit is an important block in any digital circuit. It improves the parallel addition process. Since the number of bits in various digital circuits is being increased, as such, we need millions of transistors to perform several functions in parallel. But it increases the need for surface area, power consumption, noise, and other factors. Therefore, we need to reduce the transistor size to alleviate these problems. In this research article, we designed a 4-bit carry look ahead full adder circuit at several technology nodes using Proteus and then simulated it in Microwind. The designed circuit and layout are presented here. Besides, various operational factors are obtained to observe the benefits of the transistors' size decrement. The layouts are converted and simulated at130 nm.....

Key Words: CMOS; Carry Look Ahead (CLA)Full Adder; Technology Node; VLSI; Area; Power Consumption; Noise; Delay..

[1]. S. Purohit and M. Margala, ―Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance‖ IEEE Transaction Very Large Scale Integration (VLSI) Systems, Vol. 20, no.7, pp.1327-1331, July 2012.
[2]. B. R. Zeydel, D. Baran, V. G. Oklobdzija, ―Energy -Efficient Design Methodologies: High-Performance VLSI Adders‖ IEEE Journal of solid-state circuits, Vol. 45, no. 6, pp.1220-1233, June 2010.
[3]. R. Yousuf and Najeeb-ud-din, ―Synthesis of Carry Select Adder in 65 nm FPGA‖ IEEE Region 10 conference, pp.1-6,2008.
[4]. A. M. Shams, T. W. Darwish, and M. A. Bayomui, "Performance analysis of low power 1 -bit CMOS full adder cells,‟ IEEE Transactions on Very Large Scale Integration (VLSI) Systems," Vol. 10, Issue 1, February 2002.
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ABSTRACT: Physical design is process of transforming RTL netlist into a layout which is manufacture-able [GDS or GDSII]. An efficient physical design flow is typically divided into five major steps: floorplanning, placement, clock tree synthesis, routing and timing closure. Power optimization is always one of the most important design objectives in modern nanometer IC design. System clock signal in electronics product consumes the important part of dynamic power, among them 70% is spent by clock buffers. This critical problem can be optimized using a technique namely clock gating. Recent studies have shown that applying MBFF is an effective means in reducing clock network power. This paper uses MBFF technique to optimize dynamic power and later clock gating on the same design to achieve better results. The aim of this project is to converge the Server SoC Partition and implement low power techniques such as MBFF and clock gating, to reduce power without degrading timing to a great extent..

Keywords: MBFF; clock gating, dynamic power; power reduction; low power;

[1]. Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri, Nabil Hmina "Usage and impact of multi-bit flip-flops low power methodology on physical implementation", 4th International Conference on Optimization and Applications (ICOA), DOI: 10.1109/ICOA.2018.8370498, 26-27 April 2018
[2]. Madhushree and Niju Rajan, "Dynamic Power Optimization Using Look- Ahead Clock Gating Technique", 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India.
[3]. Mark Po-Hung Lin, Chih-Cheng Hsu, and Yu-Chuan Chen, "Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization", IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 34, No. 2, February 2015
[4]. Jitesh Shinde, S. S. Salankar, "Clock gating — A power optimizing technique for VLSI circuits", Annual IEEE India Conference.

ABSTRACT: A simple version of the EKV MOSFET model is implemented in Verilog-A and tested with Tanner EDA software suite using S-Edit and T-Spice. The process of model development in Verilog-A and its integration into the software's library is discussed in detail. The aim of this work is to present the advantages of analog modeling with hardware description languages, especially when developing nonlinear device models, and to present the details of implementing a Verilog-A EKV MOSFET model in the simulator.

Keywords – EKV MOSFET, Verilog-A, S-Edit, T-Spice, Tanner-EDA

[1] G. P. Patsis, MOSFET EKV Verilog-A Model Implementation in Genesys, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 1, 2018, pp. 73-86.
[2] G. P. Patsis, Process-simulation-flow and metrology of VLSI layout fine-features, IOSR Journal of VLSI and Signal Processing, vol. 7, no. 6, 2017, 23-28.
[3] G. P. Patsis, VHDL-AMS macromodels of MOSFET. Consideration of gate length variability and single-electron-transistors, IOSR Journal of VLSI and Signal Processing , vol. 7, no. 6, 2017, 29-33
[4] G. P. Patsis, Basic topologies of MOS single-stage amplifiers. DC analysis for maximum input-voltage swing and amplification, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 1, 2018, 47-59.
[5] G. P. Patsis, Educational Introduction to VLSI Layout Design with Microwind, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 5, 2018, 18-29.

ABSTRACT: The integrated circuit/system designers are faced with problems that involves nano-scale devices with far less than ideal characteristics, very high integration densities (i.e. giga-scale complexity), very high operation speeds and data transmission rates, and system-level integration of analog and digital functions. The single-electron tunnelling (SET) devices might be scaled down almost to the molecular level. Gate length variability due to intra or inter die variations can lead to considerable mismatch between devices even inside the same chip. This variability has to be considered in detail and new device models should be developed, aiming in modelling its effects.......

Keywords: mosfet, line-width-roughness, vhdl-ams, digital-gates, single-electron-transistor, coulombblockage, compact-device-modelling

[1]. Y. S. Yu, H. S. Lee, and S. W. Hwang, SPICE Macro-Modelling for the Compact Simulation of Single Electron Circuits, J.
Korean Phys. Soc. 33, 1998, 269.
[2]. G. P. Patsis, Modelling MOSFET gate length variability for future technology node, Phys. Stat. Sol. (a) 205 (11), 2008, 2541-2543.
Ansys site: http://www.ansys.com/

ABSTRACT: Analyzing the characteristics of an ECG signal plays a vital role in the detection of various Cardiovascular Diseases (CVDs). However the analysis of ECG signal is not a simple task. In this paper a broad survey is carried out over various approaches focused to analyze the characteristics of ECG signal to perform automatic Cardiac Arrhythmia detection. Initially, the details of ECG acquisition, Characteristics of ECG and the possible arrhythmias based on the abnormalities in the ECG signal are discussed. Based on the step by step execution of the system model, all the approaches are classified as preprocessing approaches, feature extraction approaches and classification approaches. These approaches.......

Keywords: ECG, Cardiovascular Diseases, Cardiac Arrhythmia, Feature Extraction, MIT-BIH

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