iosr-JVSP   Volume-2 ~ Issue-5

ABSTRACT: Speaker verification is the method of automatically identifying who is speaking on the basis of individual information integrated in speech waves. An important application of speaker verification is for forensic purposes. Speaker verification has seen an appealing research field for the last decades which still yields a number of unsolved problems. Many algorithms have been developed to accomplish, some of which include Gaussian Mixture Model (GMM), Hidden Markov Model (HMM), Artificial Neural Network. All the before mentioned algorithms serve the feature matching mechanism while the MFCC (Mel Frequency Cepstral Coefficients) are the features extracted of a voice signal. The Mel scale is mainly based on the study of observing the pitch or frequency perceived by the human.The simplest of the algorithms is calculating the distortion distance between the various codebooks of the speakers, but its efficiency is less compared to other algorithms. Here, we have tried to increase the efficiency of this method. The two phases of this system is the training phase and the testing phase. The training phase involves the feature extraction using MFCC and storing the codebooks in the database. The testing phase involves all these plus the distortion distance calculation using the codebook of the unknown speaker against all the speakers whose codebook is already stored in the database and is verified if the speaker matches with the claimed identity.

Keywords: Distortion Distance, Feature Extraction, Feature Matching, MFCC, Mel scale, Speaker Recognition, Training Phase, Testing Phase, Vector Quantisation

[1]. Journal paper: Sujit Kumar Behera, Jatindra Kumar Singh, Speaker Verfication using Mel frequency cepstral coefficient and artificial neural network
[2]. Journal paper: Mohd Zaizu Ilyas, Salina Abdul Samad, Aini Hussain, Khairul Anuar Ishak, Speaker Verification using Vector Quantization and Hidden Markov Model.
[3]. Thesis submitted on Kernel Based Learning Methods for Pattern and Feature Analysis by WU Zhili, Hong Kong University.
[4]. The physiology of speech production
[5]. Paper by Md. Rashidul Hasan, Mustafa Jamil, Md. Golam Rabbai Md. Saifur Rahman on Speaker Identification Using Mel Frequency Cepstral Coefficients.
[6]. Review of different techniques for speaker recognition system by Bansod.N.S., Seema Kawathekar and Dabhade S.B.
[7]. ICME 2004 Tutorial on Audio Feature Extraction by George Tzanetakis, University of Victoria, Canada.
[8]. About the voice: http://www.lionsvoiceclinic.umn.edu/page2.htm (last viewed May, 2013).

ABSTRACT: A complex number can be interpreted as a vector in imaginary plane. The vector rotation in the x/y plane can be realized by rotating a vector through a series of elementary angles. These elementary angles are chosen such that the vector rotation through each of them may be approximated easily with a simple shift and add operation, and their algebraic sum approaches the required rotation angle. This can be exercised by CORDIC ('CO-ordinate Rotation Digital Computer) algorithm in rotation mode. In this paper, we have proposed a pipelined architecture new memory less z-path eliminated CORDIC algorithm for FFT computation. Pipelined architecture by pre computation of direction of micro rotation, radix-4 number representation, and the angle generator has been processed in terms of hardware complexity, iteration delay and memory reduction. Comparison of the proposed architecture with the conventional radix-4 architectures is elaborated. The proposed algorithm also exercises an addressing scheme and the associated angle generator logic in order to eliminate the ROM usage for bottling the twiddle factors. It incorporates parallelism and pipe line processing. The latency of the system is n/2 clock cycles. The throughput rate is one valid result per eight clock cycles. Additionally VLSI implementation on Virtex -4 FPGA is done. The implemented design operates at 450.654 MHZ of clock rate with a power consumption of 175.90mW.

Keywords-CORDIC, , FPGA, latency, Radix-4 , memory less systems, speed, throughput.

[1] Sathish Sharma , Implementation of ParaCORDIC Algorithm and it's Applications in Satellite Communication ,2009 . International conference in Advances in Recent in Technologies in communication & computing
[2] Meng Qian, Applications of CORDIC Algorithm to Neural Networks in VLSI Design ,IMACS 2006,Beijing, China
[3] Javier Valls, The use of CORDIC in Software Defined Radios: A Tutorial, IEEE Communications Magazine, Sep ‗2006
[4] Ayan Benerjee, Swapna Banerjee, ‗FPGA realization of a CORDIC based FFT processor for biomedical signal processing, Microprocessors and Microsystems, Feb 2011.
[5] .Bu-chin wang Digital signal processing Techniques and Applications in Radar Image processing.
[6] Bum Sikkim , Low power pipelined FFT architecture for Synthetic Aperture Radar, IEEE 39th Midwest Symposium, Circuits & Systems 1996.
[7] Sadat A , FFT for high speed OFDM wireless multimedia system, IEEE Circuits & Systems 2001 , MWSAS 2001
[8] Volder, J. (1959). The CORDIC trigonometric computing technique., IEEE Transactions on Electronic Computers
[9] B. Lakshmi , A.S. Dhar VLSI architecture for low latency radix-4 CORDIC, Elseiver Computers and Electrical Engineering, July 2011
[10] francisco j. jaime,enhanced scaling-free cordic, ieee transactions on circuits and systems—i: regular papers, vol. 57, no. 7, july 2010

ABSTRACT: The design of introduces a multi-mode transmulti- plexer (TMUX) structure capable of generating a great set of user-bandwidths and center frequencies. The structure utilizes fixed integer sampling rate conversion (SRC) blocks, Farrow- based variable interpolation and decimation structures, and variable frequency shifters. A main advantage of this TMUX is that it needs only one filter design beforehand. Specifically, the filters in the fixed integer SRC blocks as well as the subfilters of the Farrow structure are designed only once. Then, all possible combinations of bandwidths and center frequencies are obtained by properly adjusting the variable delay parameter of the Farrow-based filters and the variable parameters of the frequency shifters. The paper includes examples for demonstration. It also shows that, using the rational SRC equivalent of the Farrow- based filters, the TMUX can be described in terms of conventional multirate building blocks which may be useful in further analysis of the overall system.

Index Terms—Multi-mode communications, transmultiplexers, sampling rate conversion.

[1] Amir Eghbali, H°akan Johansson, Senior Member, IEEE, and Per L¨owenborg, Member, IEEE "A Multi-Mode Transmultiplexer Structure," IEEE Transactions on circuits and systems 02 volume 02 2008.

[2] A. Eghbali, H. Johansson, and P. Lo¨ wenborg, "An arbitrary bandwidth transmultiplexer and its application to flexible frequency-band realloca- tion networks," in Proc. European Conf. Circuit Theory Design, Seville, Spain, Aug. 2007.

[3] A. N. Akansu, P. Duhamel, L. Xueming, and M. de Courville, "Orthog- onal transmultiplexers in communication: a review," IEEE Trans. Signal Processing, vol. 46, no. 4, pp. 979–995, Apr. 1998.

[4] B. Arbesser-Rastburg, R. Bellini, F. Coromina, R. D. Gaudenzi, O. del Rio, M. Hollreiser, R. Rinaldo, P. Rinous, and A. Roederer, "R&D directions for next generation broadband multimedia systems: an ESA perspective," in Proc. 20th AIAA Int. Commun. Satellite Syst. Conf.Exhibit, Montreal, Canada, May 2002.

[5] H. Johansson and P. Lo¨ wenborg, "Flexible frequency-band reallocation drawn as shown in Fig. 6 and is similar (with some differences networks using variable oversampled complex-modulated filter banks," EURASIP Journal on Advances in Signal Processing, vol. 2007, Article ID 63714, 15 pages, 2007.

[6] P. P. Vaidyanathan, Multirate Systems and Filter Banks.Englewood Cliffs, NJ: Prentice-Hall, 1993.

[7] H. Johansson and P. Lo¨ wenborg, "On the design of adjustable fractional delay FIR filters," IEEE Trans. Circuits Syst. II, vol. 50, no. 4, pp. 164–169, Apr. 2003.

[8] H. Johansson and O. Gustafsson, "Linear-phase FIR interpolation, decimation, and M -th band filters utilizing the Farrow structure," IEEE Trans. Circuits Syst. I, vol. 52, no. 10, pp. 2197–2207, Oct. 2005.

ABSTRACT: The compression of medical images is essential for reducing the cost of data storage and transmission time which in turn helps in better utilization of Bandwidth. The demand for images, video sequences and computer animation has increased drastically over the years which have also resulted in image and video compression. Image compression is broadly classified into lossy and lossless compression. Fractal image compression (FIC) is a lossy compression method. In fractal image compression an image is coded as a set of contractive transformations in a complete metric space. The set of contractive transformations is guaranteed to produce an approximation to the original image. In this paper quad-tree FIC is implemented on different Imaging modalities like Medical Resonance (MR) Image of Brain, Computerized tomography(CT) of Bone.The quality factors like Mean Square Error (MSE) , Peak Signal–to–Noise-Ratio (PSNR) Compression ratio(CR), Encoding time and decoding time for different imaging modalities with different threshold values are analyzed in this paper. From the matlab simulated results it is observed that Quad-tree FIC works better on medical image as it provides better PSNR, CR values over the other images. This paper also includes a comparison between standard FIC and Quad-tree FIC on MR image of Brain and study of the parameters reveals that Quad-tree FIC works better than Standard FIC. Keywords— Medical Imaging Fractal image compression, Quad-tree partitioning, objective quality measures

[1] M. Barnsley, Fractals Everywhere. New York: Academic,(1988).
[2] A.E. Jacquin, "Image coding based on a fractal theory of iterated contractive image transformation", IEEE Trans. On Image Processing, 1(1): (1992
[3] Y. Fisher, Fractal Image Compression: Theory and Application. New York: Springer-Verlag, (1994).
[4] A.E Jacquin, "Fractal image coding: A review", Proceeding of tile IEEE, 81(10): (1993)
[5] M.S.Soyjaudah and I.Jahmeerbacus "Fractal image compression using quad-tree partitioning" International Journal of Electrical Engineering Education 39/1
[6] Dr. Fakhiraldeen H. Ali Quad-tree Fractal Image Compression University of Mosul
[7] Sumathi Poobaland G. Ravindran, "Arriving at an OptimumValue of Tolerance Factor for Compressing Medical Images," world Academy of Science,Engineering and Technology, vol. 24, pp. 169-173, 2006.
[8] Pamela Cosman, Gray R.M. and Olshen A.(1994b)"Evaluating Quality of Compressed Medical Images: SNR, Subjective Rating and Diagnostic Accuracy‟, Proc. of the IEEE, Vol. 82, pp. 920-931.
[9] S. Bhavani et. al. / (IJCSE) International Journal on Computer Science and Engineering Vol. 02, No. 05, 2010, 1429-1434 A Survey On Coding Algorithms In Medical Image compression

ABSTRACT: The paper introduces the SOI technology with brief design description and the factors that help in developing low power. The paper also presents the low power generation in partially and fully depleted SOI. And finally gives the superiority factors over bulk CMOS technology. The focus of this article is to present an overview of SOI technology applied to design of a special class of ultra low power devices supervisory circuits. Such circuits are emerging as prime candidates for development using advanced SOI technology processes.

Key Words: Low power, SOI, Delays, Bulk CMOS

[1]. I.Z. Mitrovic, O. Buiu, S. Hall, D.M. Bagnall , P. Ashburn, "Review of SiGe HBTs on SOI", Solid-State Electron, Vol. No. 49,, (2005), pp. 1556–1567.
[2]. N. Lukyanchikova, N. Garbar, A. Smolanka, M. Lokshin, S. Hall , O. Buiu et al., "1/f noise andgeneration/recombination noise in SiGe HBTs on SOI, IEEE Trans Electronic Device,Vol. No. 52, (2005), pp. 1468–1477.
[3]. J.A. Babcock, W.M. Huang, J.M. Ford, D. Ngo, D.J. Spooner and S. Cheng, Low-frequency noise dependence of TFSOI BiCMOS for low power RF mixed-mode applications, IEDM Tech Dig, The IEEE, New York (1996), p. 133.
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[6]. V. Subramanian, A. Mercha, A. Dixit, K.G. Anil, M. Jurczak , K. De Meyer , "Geometry dependence of 1/f noise in n- and p-channel MuGFETs." ,18th international conference on noise and fluctuations – ICNF, (2005), p. 279.
[7]. V. Subramanian, B. Parvais, J. Borremans, A. Mercha, D. Linten ,P. Wambacq "Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs", IEDM Tech Dig, (2005), p. 898.
[8]. E. Simoen, P.I.L. Smeys ,C. Claeys, "The low-frequency noise overshoot in partially depleted n-channel silicon-on-insulator twin-MOSTs", IEEE Trans Electronic Device,Vol. No. 41, (1994), pp. 1972–1977.
[9]. Simoen E, Claeys C, Lukyanchikova N, Garbar N,A. Smolanka "Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs." ULIS 2006 – sixth international conference on ultimate integration of silicon; 2006. p. 113.
[10]. Akarvardar K, Cristoloveanu S, Dufrene B, Gentil P, Schrimpf RD, Blalock BJ, et al. Evidence for reduction of noise and radiation effects in G4-FET depletion-all-around operation. , ESSDERC; 2005. p. 89.

ABSTRACT: The efficiency of a system mainly depends on the performance of internal components present in the system. The internal components should be designed in such a way that they consume low power with high speed. Lot of components is in circuits including full-adder. This is mainly used in processors. A new Pass transistor full adder circuit is implemented in this paper. The main idea is to introduce the design of high performance and based pass transistor full adders which acquires less area and transistor count. The high performance of pass transistor low power full adder circuit is designed and the simulation has been carried out on Tanner EDA Tool. The result shows that the proposed full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and increases the speed. In this paper CMOS full adder circuits are designed to reduce the power and area and to increase the speed of operation in arithmetic application. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem

Keywords: Arithmetic, Full-adder, Power consumption, High-speed.

[1]. A. M. Shams and M. Bayoumi, "Performance evaluation of 1-bit CMOS adder cells," in Proc. IEEE ISCAS, Orlando, FL, May
1999,vol. 1, pp. 27–30.
[2]. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, ASystem Perspective. Reading, MA: Addison-Wesley, 1988, ch. 5.
[3]. K. M. Chu and D. Pulfrey, "A comparison of CMOScircuittechniques:Differentialcascode voltage switch logic versus conventional
logic,"IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528–532, Aug.1987.
[4]. K. Yano, K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi,and A. Shimizu, "A 3.8 ns CMOS 16*16 -b multiplier
using complementary pass-transistor logic," IEEE J. Solid-State Circuits, vol.25, no. 2, pp. 388–395, Apr. 1990.
[5]. M. Suzuki, M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A.Shimizu, K. Sasaki, and Y. Nakagome, "A 1.5 ns 32 -b CMOS ALU
in double pass-transistor logic," IEEE J. Solid-State Circuits, vol. 28,no. 11, pp. 1145–1150, Nov. 1993.
[6]. R. Zimmerman and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol.
32, no.7, pp. 1079–1090, Jul. 1997.
[7]. M. Zhang, J. Gu, and C. H. Chang, "A novel hybrid pass logic with static CMOS output drive full-adder cell," in Proc. IEEE Int.
Symp.Circuits Syst., May 2003, pp. 317–320.
[8]. C. Chang, J. Gu, and M. Zhang, "A reviewof 0.18-μm full adder performances for tree structured arithmetic circuits," IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
[9]. S. Goel, A. Kumar, and M. Bayoumi, "Design of robust, energy-efficient full adders for deep-sub micrometer design using hybrid-
CMOS logic style," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14,no. 12, pp. 1309–1320, Dec. 2006.
[10]. S. Agarwal, V. K. Pavankumar, and R. Yokesh, "Energy-efficient high performance circuits for arithmetic units," in Proc. 2nd Int.
Conf. VLSI Des., Jan. 2008, pp. 371–376.

ABSTRACT: In block based motion estimation, each frame is divided into macroblocks and motion estimation is performed macroblock wise. It has high computational cost. In this paper, a block based motion estimation technique using color segmentation has been proposed which has single block for each object and motion estimation based on diamond search technique has been used to compute motion vectors. Experimental results show that the performance of Diamond search technique using color segmentation is better than conventional Diamond Search Technique in terms of PSNR, average number of search points and compression ratio.

Keywords: colour based segmentation, diamond search, macro block, motion vector, video compression.

[1]. S. Zhu and K.K. Ma, "A new diamond search algorithm for fast block matching motion estimation," in IEEE Transactions On Image Processing, Vol. 9, 287-290, 2000
[2]. J. Jain and A. Jain, "Displacement measurement and its application in Interframe image coding," IEEE Trans. Commun., vol. COMM-29, pp. 1799–1808, Dec. 1981.
[3]. T. Koga, K. Iinuma, A. Hirano, Y. Iijima, and T. Ishiguro, "Motion compensated interframe coding for video conferencing," in Proc. Nat. Telecommun. Conf., New Orleans, LA, Nov. 29–Dec. 3 1981, pp.G5.3.1–5.3.5.
[4]. M. Ghanbari, "The cross-search algorithm for motion estimation," IEEE Trans. Commun., vol. 38, pp. 950–953, July 1990.
[5]. R. Li, B. Zeng, and M. L. Liou, "A new three-step search algorithm for block motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 4, pp. 438–442, Aug. 1994.
[6]. L. M. Po and W. C. Ma, "A novel four-step search algorithm for fast block motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 6, pp. 313–317, June 1996.
[7]. L. K. Liu and E. Feig, "A block-based gradient descent search algorithm for block motion estimation in video coding," IEEE Trans. Circuits Syst. Video Technol., vol. 6, pp. 419–423, Aug. 1996.
[8]. S. Zhu and K.-K. Ma, "A new diamond search algorithm for fast block matching motion estimation," in Proc. Int. Conf. Inform., Commun.,Signal Process., Singapore, Sept. 9–12, 1997, pp. 292–296.
[9]. C.Zhu, X. Lin and L. P. Chau, "Hexagon based search pattern for fast block motion estimation," in IEEE Transactions in circuit systems and video technology, Vol 12, 349-355, 2002.
[10]. C.Zhu, X. Lin, L. P. Chau,. and L. M. Po, "Enhanced hexagonal search for fast block motion estimation," in IEEE Transactions in circuit systems and video technology, Vol 14, 1210-1214, 2004.

ABSTRACT: A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in general processors. This paper proposes the design of 8x8 bit Vedic multiplier based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. The proposed architecture is for two 8-bit numbers, the multiplier and multiplicand each arc grouped as 4-bit numbers; so that it decomposes into 4x4 multiplication modules. This gives chance for modular design where smaller blocks can be used to design the bigger one. Further, the VHDL coding of Urdhava Tiryakbhyam sutra for 8x8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool have been done.

Keywords- FPGA, Urdhua Tiryagbhyam sutra, Vedic mathematics, Xilinx.

[1] Swami Bharati Krshna Tirthaji, Vedic Mathematics. (Delhi: Motilal Banarsidass Publishers, 1965).

[2] A. Haveliya "A Novel Design for High Speed Multiplier for Digital Signal Processing Applications (Ancient Indian Vedic mathematics approach", International Journal of Technology And Engineering System(IJTES), 2 (1), 2011.

[3] H. S. Dhillon and A. Mitra "A Digital Multiplier Architecture using Urdhava Tiryakbhyam Sutra oj Vedic Mathematics" IEEE Conference Proceedings, 2008.

[4] P. Mehta, D. Gawali "Conventional versus Vedic mathematical method for Hardware implementation of a multiplier" International Conference on Advances in Computing, Control, and Telecommunication Technologies, 2009.

[5] H. Thapliyal, S. Kotiyal and M.B. Srinivas, "Design and Analysis of a Novel Parallel Square and Cube Architecture Based on Ancient Indian Vedic Mathematics", Proceedings on 48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2005.

[6] S. Akhtar, "VHDL Implementation of Fast NxN multiplier Base on Vedic Mathematics," Jaypee Institute of Information Technology University, Noida, 2011307 U.P, India, IEEE, 2007.

[7] L. Sriraman, T.N. Prabakar.''Design and Implementation of two variable Multiplier using KCM and Vedic Mathematics", 1st International Conference on Recent Advances in Information Technology IEEE, 2012.

[8] P. Verma, K.K. Mehta, ''Implementation of an efficient multiplier based on Vedic Mathematics using EDA Tool'', International Journal of Engineering and Advance Technology (IJEAT) ISSN : 1 (5), 2012, 2249-8958.

[9] L. G. Moses. S and M Thilagar, "VLSI Implementation of high speed DSP algorithms using Vedic Mathematics.'' International Journal of Computers Communication and Information System. 2 (1), 2010, 0976 – 1349.

[10] B.C. Paul, F.S. Fujita., M. Okajima. "ROM Based logic (RBL) Design, A low- power 16 bit Multiplier", IEEE Journal of solid State Circuits, 44 (11), 2009, 2935-42.

ABSTRACT:Low power has emerged as a principle theme in today electronic industry. Energy efficiency is one of the most important features of modern electronic systems designed for high speed and portable applications. The power consumption of the electronic devices can be reduced by using different design styles. Adiabatic logic style is said to be an attractive solution for such low power electronic applications. This paper presents an energy efficient technique for digital circuits that uses adiabatic logic. The proposed technique has less power dissipation compared to the conventional CMOS design style. This paper evaluates the 2x2 bit square in different adiabatic logic styles and their results were compared with the conventional CMOS design. The simulation results indicate that the proposed technique is advantageous in many of the low power digital applications.

Keywords: Adiabatic, Charge recovery, low power, energy efficient, digital circuits, sinusoidal power clock.

[1] B. Dilli Kumar, M. Bharathi, "Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic" in International Journal of Engineering Trends and Technology, 2013.

[2] Atul Kumar Maurya and Ganesh Kumar, "Adiabatic Logic: Energy Efficient Technique for VLSI Applications", International Conference on Computer& Communication Technology (ICCCT)-2011.

[3] Vojin G. Oklobd"zija, Dragan Maksimovi' c, "Pass-Transistor Adiabatic Logic Using Single Power-Clock Supply ", IEEE Transactions on Circuits and Systems, Vol. 44, No. 10, October 1997.

[4] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low power CMOS digital design,'' IEEE J. Solid-State Circ., vol. 27, no. 4, pp.473-484, Apr. 1992.

[5] T. Indermauer and M. Horowitz, "Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power Design," Technical Digest IEEE Sym. Low Power Electronics, San Diego, pp. 102-103, Oct. 2002.

[6] Arsalan, M. Shams, M., "Charge-recovery power clock generators for adiabatic logic circuits", 18th International Conference on VLSI Design, pp. 171- 174, 3-7 January 2005.

[7] Dragan Maksimovic et al, "Clocked CMOS adiabatic Logic with Integrated Single Phase Power Clock Supply", IEEE Transactions on VLSI Systems, vol 8, No 4, pp 460-463, August 2000.

[8] W.C. Athas, L. Svensson, J.G. Koller et ,N.Tzartzanis and E.Y.Chou: "Low-power Digital Systems Bared on Adiabatic-switching Principles". IEEE Transactions on VLSI Systems. Vol. 2, No. 4, pp. 398-407 December. 1994.

[9] Satyam Mandavilli, Prashanth Paramahans " An Efficient Adiabatic Circuit Design Approach for" International Journal of Recent Trends in Engineering, Vol 2, No. 1, November 2009 Low Power Applications.

[9] A. Vetuli, S. Di Pascoli, and L.M. Reyneri, "Positive feedback inadiabatic logic," Electron.Lett.,vol.32, pp.1867-1869, Sept. 1996. [10] N. Anuar, Y. Takahashi, T. Sekine, "Two phase clocked adiabatic static CMOS logic," proc. IEEE SOCC 2009, pp. 83-86, Oct. 2009.

ABSTRACT: Error detection is important whenever there is a non-zero chance of data getting corrupted. A Cyclic Redundancy Check (CRC) is the remainder, or residue, of binary division of a potentially long message, by a CRC polynomial. This technique is ubiquitously employed in communication and storage applications due to its effectiveness at detecting errors and malicious tampering. The hardware implementation of a bit-wise CRC is a simple linear feedback shift register. Such a circuit is very simple and can run at very high clock speeds, but it requires the stream to be bit-serial. This means that 'n' clock cycles will be required to calculate the CRC values for an n-bit data stream. This latency is intolerable in many high speed data networking applications where data frames need to be processed at high speed and hence implementation of CRC generation and checking on a parallel stream of data becomes desirable. This paper presents implementation of parallel Cyclic Redundancy Check (CRC) based upon DSP algorithms of pipelining, retiming and unfolding. The architectures are first pipelined to reduce the iteration bound by using novel look-ahead techniques and then unfolded and retimed to design high speed parallel circuits. This paper presents the comparison between the parallel implementation of CRC-9 and its serial implementation. It also shows that parallel implementation uses less number of clock cycles than the serial implementation of CRC-9 thereby increasing the speed of the architecture. This paper is implemented using Verilog hardware description language, simulated using Xilinx ISE tools and synthesized using Cadence tools.

Keywords - Cyclic Redundancy Check (CRC), Pipelining, Retiming, Unfolding

[1] G. Campobello, G. Patane, and M. Russo, "Parallel CRC realization," IEEE Trans. Comput., vol. 52, no. 10, pp. 1312–1319, Oct. 2003.
[2] T.B. Pei and C. Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. Commun., vol. 40, no. 4, pp. 653–657, Apr. 1992.
[3] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. Hoboken, NJ: Wiley, 1999.
[4] T. V. Ramabadran and S.S. Gaitonde, " A tutorial on CRC computations," IEEE Micro, Vol.8 no.4, pp. 62-75, Aug.1988.
[5] X. Zhang and K. K. Parhi, "High-speed architectures for parallel long BCH encoders," in Proc. ACM Great Lakes Symp. VLSI, Boston, MA, Apr. 2004, pp. 1–6.
[6] K. K. Parhi, " Eliminating the fanout bottleneck in parallel long BCH encoders," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 3, pp. 512-516, Mar. 2004.