IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Mar - Apr 2014 Vol 4 - Issue 2

Version 1 Version 2 Version 3 Version 4

Paper Type : Research Paper
Title : Image Registration and Wavelet Based Hybrid Image Fusion
Country : India
Authors : Mrs.Disha S Bhosle, Mrs. Kanchan S Gorde
: 10.9790/4200-04210105    logo

ABSTRACT: Image fusion is to integrate complementary multisensor, multitemporal and multiview data into one new image containing data of quality which cannot be achieved otherwise. As optical lenses in capturing device have limited depth-of-focus , it is sometime not possible to obtain an image that contains all relevant objects, in focus. To achieve all objects in focus, a fusion process is required which focuses all objects.The solution to this problem is the new architecture called Hybrid Image Fusion which .involves physical image alignment by using image registration ,then applying DWT. In the intermediate stage the images are decomposed and further fused to obtained hybrid image by using pixel rules.

Keywords: D.W.T , Image Registration, Hybrid Image Fusion , Multiresolution , Pixel rules

[1] Gonzalo Pajares, Jesus Manuel De la Cruz, A Wave-based image fusion tutorial The Journal of The Pattern Recognition Society,10.1010/j.patcog.2004.03.010.
[2] Barbara Zitova,Jan Fluseer, Image Registration Method-A Survey Image and Vision Computing 21(2003)977-1000.
[3] Medha V. Wyawahare, Dr. Pradeep M. Patil, and Hemant K. Abhyankar, Image Registration Techniques: An overview International Journal of Signal Processing, Image Processing and Pattern Recognition Vol. 2, No.3, September 2009.
[4] Jan Flusser, Filip ˇSroubek, and Barbara Zitov´a, Image Fusion:Principles, Methods, and Tutorial EUSIPCO 2007 Lecture Notes.
[5] Susmitha Vekkot and Pancham Shukla, A Novel Architecture for Wavelet based Image Fusion, Journal of World Academy of Science , Engineering and Technology, 2009. pp. 32-33.
[6] Stavri Nikolov, Paul Hill, David Bull, Nishan Canagarajah, WAVELETS FOR IMAGE FUSION, Image Communications GroupCentre for Communications Research University of Bristol
[7] Dr.S.S.Bedi1, Mrs.Jyoti Agarwal2, Pankaj Agarwal, Image Fusion Techniques and Quality Assessment Parameters for Clinical Diagnosis: A Review, International Journal of Advanced Research in Computer and Communication Engineering Vol. 2, Issue 2, February 2013
[8] Anjali Malviya, S.G. Bhirud, Image Fusion of Digital Images, International.Journal of Recent Trends in Engineering, Vol 2,No 3, Nov. 2009.pp.146-148.

Paper Type : Research Paper
Title : Evaluation of Stability and Optimum Energy Consumption In Wireless Sensor Network
Country : India
Authors : A.Kalyan, K. Chaitanya, B.N.S.Chaitanya, R. Divya kanti
: 10.9790/4200-04210615    logo

ABSTRACT: Sensor network consists of tiny sensors and actuators with general purpose computing elements to cooperatively monitor physical or environmental conditions such as temperature, pressure, etc. Wireless Sensor Networks are uniquely characterized by properties like limited power they can harvest or store, dynamic network topology, large scale of deployment. To increase the network lifetime we used energy efficient communication protocol known as Low Energy Adaptive Clustering Hierarchy (LEACH). Low Energy Adaptive Clustering Hierarchy (LEACH) is an energy-efficient hierarchical-based routing protocol. Our prime focus was on the analysis of LEACH based upon parameter network lifetime reducing the power consumption of wireless sensor networks.

[1] L. B. Oliveira E. Habib H. C. Wong A. C. Ferreira, M. A. Vilaa and A. A. Loureiro. Security of cluster-based communication protocols for wireless sensor networks. In 4th IEEE International Conference on Networking (ICN05), volume Lecture Notes in Computer Science, pages 449{458, Washington, DC, USA, 2005.
[2] Jamal N. Al-karaki and Ahmed E. Kamal. Routing techniques in wireless sensor networks: A survey. IEEE Wireless Communications, 11:6-28, 2004.
[3] Y. Geng C. Hong-bing and H. Su-jun. Nhrpa: a novel hierarchical routing protocol algorithm for wireless sensor networks. China Universities of Posts and Telecommunications, September 2008.
[4] G. Hu D. Wu and G. Ni. Research and improve on secure routing protocols in wireless sensor networks. In 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC 2008).
[5] Wendi Rabiner Heinzelman, Anantha Ch, and Hari Balakrishnan. Energy-efficient communication protocol for wireless microsensor networks. pages 3005-3014, 2000.

Paper Type : Research Paper
Title : Designing of signed multiplier without 2's compliment method
Country : India
Authors : Shaik.Moulali, Dileep.G,kadhar basha
: 10.9790/4200-04211622    logo

ABSTRACT:Two's complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partial product array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width two's complement multipliers for high-performance embedded cores.

[1]. M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann Publishers, 2003.
[2]. S.K. Hsu, S.K. Mathew, M.A. Anders, B.R. Zeydel, V.G. Oklobdzija, R.K. Krishnamurthy, and S.Y. Borkar, "A 110GOPS/ W 16-Bit Multiplier and Reconfigurable PLA Loop in 90-nm CMOS," IEEE J. Solid State Circuits, vol. 41, no. 1, pp. 256-264, Jan. 2006.
[3]. H. Kaul, M.A. Anders, S.K. Mathew, S.K. Hsu, A. Agarwal, R.K. Krishnamurthy, and S. Borkar, "A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS," IEEE J. Solid State Circuits, vol. 45, no. 1, pp. 95- 101, Jan. 2010.

Paper Type : Research Paper
Title : Design and Simulation of Two Channel QMF Filter Bank using Equiripple Technique.
Country : India
Authors : Meena Kohli, Rajesh Mehra
: 10.9790/4200-04212328    logo

ABSTRACT:In this paper a design of a two channel FIR QMF bank for perfect reconstruction is presented. The QMF design has multicriterion constraints such as minimal of reconstruction error and minimal of iterations are among the most important problems in filter bank design. The main problem of filter bank design is to find adequate coefficients for the prototype filter H0 such that the prototype filter has minimum error in stopband, passband and transition band. The proposed QMF filter bank has been developed using equiripple linear phase FIR filters with MATLAB. The developed equiripple linear phase filter bank performance has been compared with kaiser window based filter bank in terms of peak reconstruction error. The results show that equiripple based filter bank provides better PRE ranging from 16.45% to 17.31% as compared to kaiser window based filter bank.

Keywords: Equiripple FIR filters, Kaiser Window, Perfect Reconstruction, QMF Filter bank.

[1] S. C. Chan, C. K. S. Pun, K. L. Ho,"New design and realization techniques for a class of perfect reconstruction two-channel FIR filter banks and wavelet bases", IEEE Transactions Signal Processing, Vol. 52, No. 7, Pp. 2135–2141, 2004.
[2] R. Bregovic and T. Saramaki, "A general-purpose optimization approach for designing two-channel FIR filter banks", IEEE Transactions on signal processing, vol. 51, no. 7, , Pp. 3303-3314, July 2003.
[3] S. C. Chan and S. S. Yin, "On the design of low delay nearly-PR and PR FIR cosine modulated filter banks having approximate cosine-roll off transition band", in Proc. EUSIPCO, Pp. 1253–1256 ,Sep. 2004.
[4] Ram Kumar Soni, Alok Jain, and Rajiv Saxena, "New Efficient Iterative Optimization Algorithm to Design the Two Channel QMF Bank", World Academy of Science, Engineering and Technology, Vol. 24, Pp 56-60, 2008.
[5] T Ghosh, A.; Giri, R.; Chowdhury, A.; Das, S.; Abraham, A. "Two-Channel Quadrature Mirror Bank Filter Design Using a Fitness- Adaptive Differential Evolution Algorithm", Nature and Biologically Inspired Computing (NaBIC), Second World Congress , Pp 634 – 641 , 2010.

Paper Type : Research Paper
Title : Analysis of Different Multiplication Algorithms & FPGA Implementation
Country : India
Authors : K.Harika, B.V.Swetha, B.Renuka, D.Lakshman Rao, S.Sridhar
: 10.9790/4200-04212935    logo

ABSTRACT:As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today's VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. Multiplication is a basic arithmetic operation which is present in any part of the digital computer especially in signal processing systems. Different techniques are used for multiplication. Some of the techniques are CSA, CSD, Booth's, Grid, Lattice, Combinational, Sequential, Array, Vedic, Wallace-tree etc.

Keywords: Multiplier, VHDL, FPGA

1] GarimaTiwari "Analysis, Verification and FPGA Implementation of Low Power Multiplier".
[2] Kripa Mathew, S.AshaLatha, T.Ravi, E.Logashanmugam "design and analysis of an Array Multiplier using an Area Efficient full adder cell in 32 nm CMOS Technology".
[3] ChakibAlaoui "Design and Simulation of a Modified Architecture of Carrysave Adder".
[4] DeepaliChandel,GaganKumawat, PranayLahoty, VidhiVartChandrodaya, Shailendra Sharma.International Journal of Emerging Technology and Advanced Engineering Volume 3, Issue 3, March 2013"Booth Multiplier: Ease of multiplication".
[5] International Journal of Engineering Science InventionShaik.Kalisha Baba, D.Rajaramesh "Design and Implementation of Advanced Modified Booth Encoding Multiplier".

Paper Type : Research Paper
Title : A Fault Analysis in Reversible Sequential Circuits
Country : India
Authors : B.Anuradha, S.Sivakumar
: 10.9790/4200-04213642    logo

ABSTRACT:In this paper,the researchers propose the design of reversible circuits using reversible gates.Reversible logic is implemented in reversible circuits.Reversible logic is mostly preferred due to less heat dissipation.Conservative logic gates can be designed in any sequential circuits and can be tested using two test vectors.The significance of proposed work lies in the design of reversible sequential circuits and their equivalent circuits for maximum fault coverage.The design of reversible sequential circuits using Toffoli gate and Peres gate is proposed in this literature.The design of Toffoli and Peres equivalent circuits is proposed first time in this literature, in order to achieve maximum fault coverage. The proposed Toffoli and Peresgates surpass the Fredkin gate and MXCQCA gate in terms of area, number of gates and timing. The simulation and coding is performed using cadence tool.

Keywords: Reversible logic, Peres gate, Toffoli gate, Feynman gate, latches.

[1] Dmitri Maslov, Gerhard W.Dueck, and D.Micheal miller,"Toffoli network synthesis with Templates", 2004
[2] Vivek V.shende,Aditya K.Prasad,Igor L.Markov and John P.Hayes,"Synthesis of reversible logic circuits",IEEE trans,Vol.22.,No.6.,Jun 2003
[3] Himanshu Thapiyal and M.B.Srinivas,"A Beginning in the Reversible logic synthesis of sequential circuits", IEEE trans, 2005
[4] J.E.Rice,"The State of reversible logic synthesis", sep 2005.
[5] Sivakumar sastry hari, shyam shroff, sk.Noor Mahammad and v.Kamakoti","Efficient building blocks for sequential circuit design", IEEE trans, 2006.
[6] Pallav gupta, Abhinav Agrawal and Niraj k.Jha,"An Algorithm for synthesis of reversible logic circuits", IEEE trans, Vol.25. No.11, Nov 2006.

Paper Type : Research Paper
Title : Design of Low Power 4-bit ALU Using Adiabatic Logic
Country : India
Authors : Sriraj Dheeraj Turaga, Kundan Vanama, Rithwik Reddy Gunnuthula,
K. Jaya Datta Sai
: 10.9790/4200-04214348    logo
ABSTRACT: This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and comparisons have been made. The analysis is carried out using the industry standard EDA design environment using 250 nm technology libraries from Tanner. The results prove that the CEPAL 4-bit ALU is 55% more power efficient than the CMOS 4-bit ALU at 100MHz and at 2.5V operating voltage.
Keywords: Low Power; Static Adiabatic logic; Complementary Energy Path Adiabatic Logic (CEPAL); Power Clock(PC); Full Adder; Arithmetic Logic Unit (ALU); Multiplexer(MUX); Very Large Scale Integration(VLSI).
[1] Young moon and Deog Kyoon Jeong, "An Efficient Charge Recovery Logic Circuit," IEEE Journal of Solid State Circuits, Vol 31,No. 4, pp 514-522, April 1996.
[2] William C. Athas, Lars "J." Svensson, Jeffrey G. Koller, Nestoras Tzartzanis and Eric Ying-Chin Chou,"Low- Power Digital Systems Based on Adiabatic-Switching Principles," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 2, No. 4, pp 398-407, Dec 1994.
[3] B. Dilli Kumar and M. Bharathi, "Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic," International Journal of Engineering Trends and Technology, ISSN: 2231-5381, Vol:4, Issue 1, pp. 32-40, 2013.
[4] Ritu Sharma, Pooja Nagpal and Nidhi Sharma,"Analysis of Adiabtic NOR Gate for Power Reduction," International Journal of Latest Research in Science and Technology, ISSN (Online):2278-5299, Vol.1, Issue 2, pp 179-182 , July-August 2012.
[5] B.Sravan Kumar, Rajeshwara Mahidhar.P and N.V.G.Prasad,"Energy Efficient Adiabatic Full Adders for Future SOC‟s," International Journal of Engineering and Advanced Technology (IJEAT),ISSN: 2249 – 8958, Volume-2, Issue-2, pp. 353-356, Dec 2012.

Paper Type : Research Paper
Title : Object Counting Based On Image Processing: FPGA Approach
Country : India
Authors : Monali P. Patil, Varsha R. Ratnaparkhe
: 10.9790/4200-04214953    logo
ABSTRACT: Image processing is used in very large and expanding areas covering applications in multimedia services, arts, medicine etc. For improving the performance of image processing systems the vital solution is implementation of image processing techniques in hardware. This paper presents the objects counting such as coins, with their implementation and simulation results using a hardware description language, VHDL.
Keywords: Digital image processing, Object Counting, FPGA, Hardware design languages, VHDL.
[1] R C Gonzalez, R E Woods, "Digital Image Processing" 3rd Edition, Pearson Prentice Hall, 2004.
[2] Sparsh Mittal, Saket Gupta,and S. Dasgupta3 "FPGA: An Efficient And Promising Platform For Real-Time Image Processing Applications" Proceedings of the National Conference on Research and Development in Hardware & Systems (CSI-RDHS 2008) June 20-21, 2008, Kolkata, India.
[3] Iuliana CHIUCHISAN, Marius CERLINCA, Alin-Dan POTORAC, Adrian GRAUR "Image Enhancement Methods Approach using Verilog Hardware Description Language" 11th International Conference on Development And Application Systems, Suceava, Romania, May 17-19, 2012
[4] Stephen Bailey , "Comparison of VHDL, Verilog and SystemVerilog", Digital Simulation White Paper by Model Technology.
[5] S.Sowmya, Roy paily, "FPGA Implementation of Image Enhancement Algorithm," 978-1-4244-9799-7/111 IEEE 2011.

Paper Type : Research Paper
Title : Study of Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR–XNOR Gates
Country : India
Authors : Ravi Tiwari, Khemraj Deshmukh
: 10.9790/4200-04215460    logo
ABSTRACT: Full adders are vital components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor FA using novel XOR and XNOR gates in combination with existing ones.We have done over ten thousand HSPICE simulation runs of the entire the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while 3 new adders consistently use on average 10% less power and have higher speed compared with the previous Ten-transistor full adder and the conventional 28-T CMOS adder. One draw back of the novel adders is the threshold-voltage loss of the pass transistors.
Index Terms: Arithmetic circuit, F.A., low power, very large-scale integration (VLSI), XOR–XNOR.
[1] J. Wang, S. Fang, and W. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," IEEE J. Solid-State Circuits, vol. 29, pp. 780–786, July 1994.
[2] R. Shalem, E. John, and L. K. John, "A novel low power energy recovery full adder cell," in Proc. IEEE Great Lakes VLSI Symp., Feb. 1999, pp. 380–383.
[3] N.Weste and K. Eshraghian, Principles of CMOSVLSI Design, A System Perspective. Reading, MA: Addison-Wesley, 1993.
[4] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473–483, Apr. 1992.
[5] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, "New 4-transistor XOR and XNOR designs," Tech. Rep., Florida Atlantic Univ., Boca Raton, 1999.

Paper Type : Research Paper
Title : Design and Implementation of Adder for Modulo 2n+1 Addition
Country : India
Authors : D. Sowjanya, B. Anilkumar
: 10.9790/4200-04216167    logo
ABSTRACT: Two architectures for modulo 2n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n +1 addition. This sparse approach is enabled by the introduction of the inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed. The second architecture unifies the design of modulo 2n±1 adders. It is shown that modulo 2n+1 adders can be easily derived by straightforward modifications of modulo 2n - 1 adders with minor hardware overhead.
[1] X. Lai and J.L. Massey, "A Proposal for a New Block Encryption Standard," EUROCRYPT, D.W. Davies, ed., vol. 547, pp. 389-404, Springer, 1991.
[2] R. Zimmermann et al., "A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, Mar. 1994.
[3] H. Nozaki et al., "Implementation of RSA Algorithm Based on RNS Montgomery Multiplication," Proc. Third Int'l Workshop Cryptographic Hardware and Embedded Systems, pp. 364-376, 2001.
[4] Y. Marikina, H. Hamada, and K. Nagoya's, "Hardware Realization of High Speed Butterfly for the Maximal Length Fermat Number Transform," Trans. IECE, vol. J66-D, pp. 81-88,1983.
[5] M. Beanies, S.S. Dlay, and A.G.J. Holt, "CMOS VLSI Design of a High-Speed Fermat Number Transform Based Convolve/Correlate Using Three-Input Adders," Proc. IEE, vol. 138, no. 2,pp. 182-190, Apr. 1991.

Paper Type : Research Paper
Title : Design of Hybrid Pulsed FlipFlop Featuring Embedded logic
Country : India
Authors : N. Karthika, S. Jayanthy
: 10.9790/4200-04216874    logo
ABSTRACT: This paper introduces a novel power efficient hybrid pulsed flip-flop (HPFF) with embedded logic module (HPFF-ELM) based on transmission gate scheme. The HPFF possess a hybrid architecture that combines the merits of dynamic and static structures. The performance of modern high performance flip-flops are compared with that of HPFF at different data activity. The proposed HPFF architecture is power efficient and has the ability to incorporate logic functions into the flip-flop which forms HPFF-ELM. The performance comparisons and analysis is made in TSMC process using mentor graphics EDA tool. The HPFF and HPFF-ELM is compared with other state-of-the-art design. The performance improvements indicate that the proposed designs are well suited for modern high-performance circuits where power dissipation and area overhead are of major concern.
Key words: Flipflops, area, power dissipation, speed, delay, embedded logic.
[1] K. Absel et al., Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 1, pp. 12–29, Sep. 2013
[2] A. Hirata et al., The cross charge control flip-flop: A low-power and high-speed flip-flop suitable for mobile application SoCs, in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 306–307.
[3] M. Hansson et al., Comparative analysis of process variation impact on flip-flop power-Performance, in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp.3744– 3747.
[4] S. B. Kong et al, Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8,pp. 1263–1271, Aug. 2001.
[5] F. Klass, Semi-dynamic and dynamic flip-flops with embedded logic, inProc. Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, Jun. 1998, pp. 108–109.

Paper Type : Research Paper
Title : Convolutional Neural Network for Edge Detection in SAR Grayscale Images
Country : Egypt
Authors : Mohamed A. El-Sayed, Hamida A. M. Sennari
: 10.9790/4200-04217583    logo
ABSTRACT: Traditional differential filter-based algorithms of edge detection have the advantage of theoretical strictness, but require excessive post-processing. There is not a single edge detector that has both efficiency and reliability. Neural networks are a powerful technology for classification and edge detection of the images. This paper describes a set of concrete best practices that image analysis researchers can use to get good results with neural networks. We perform an initial exploration of the effectiveness of using Convolutional Neural Networks (CNNs) for this task. CNNs exploit spatially local correlation by enforcing a local connectivity pattern between neurons of adjacent layers. At each level, the outputs of multiple networks are fused for robust and accurate estimation. It used to realize edge detection task it takes the advantage of momentum features extraction, it can process any input image of any size with no more training required, the results are very promising when compared to both classical methods and other ANN based methods. Furthermore, we employ CNNs to estimate the scale through the accurate localization of some key points. These techniques are object-independent so that the proposed method can be applied to other types of image processing such as classification and segmentation.
Keywords: Edge detection, Convolutional Neural Networks, Max Pooling.
[1] M. Norgaard, N.K. Poulsen, O. Ravn, "Advances in derivative-free state estimation for non-linear systems," Technical Report IMM-REP-1998-15 (revised edition), Technical University of Denmark, Denmark, April 2000.
[2] L. Canny, "A computational approach to edge detection", IEEE Trans. on Pattern Analysis and Machine Intelligence, vol. 8 no. 1, pp. 679-698, 1986.
[3] D. Marr, E. Hildreth, "Theory of edge detection", Proc. of Royal Society Landon, B(207): 187-217, 1980.
[4] R. Machuca,. "Finding edges in noisy scenes", IEEE Trans. on Pattern Analysis and Machine Intelligence, 3: 103-111, 1981.
[5] F. Rosenblatt, "The Perceptron: A Probabilistic Model for Information Storage and Organization in the Brain", Cornell Aeronautical Laboratory, Psychological Review, v65, No. 6, pp. 386-408, 1958.

Paper Type : Research Paper
Title : NSCT edge Enhancement for SIFT key points extraction
Country : Algeria
Authors : Abdelkrim Ghaz, Kidiyo Kpalma, Abdennacer Bounoua
: 10.9790/4200-04218490    logo

ABSTRACT: Image registration is a key step for matching or mosaicing two or more images taken at different times, and/or with different sensors, hence the need for automatic methods arises. In this work, we present an efficient registration method based on the Non-Subsampled Contourlet Transform (NSCT) combined with the Scale Invariant Feature transform (SIFT) to extract robust local control points. Because NSCT is a shift-invariant multidirectional transform, it is used to extract edges at both spatial and directional resolutions. A comparative study is established between SIFT and NSCT-SIFT and experimental results show clearly that the proposed method (NSCT-SIFT) improves the registration accuracy.

Keywords: Registration; SIFT; NSCT, key points extraction, edge enhancement

[1]. Zitovà, B.; Flusser, I. "Image registration methods " A survey. Image Vision Comput. 2003, 21, p 973-1000.
[2]. Bentoutou, Y.; Taleb, N.; Kpalma, K.; Ronsin, J. An automatic image registration for applications in remote sensing. IEEE Trans. Geosci. Remote Sens. 2005, 43,p 2127-2137.
[3]. Do, M.N.; Vetterli, M. "Contourlet" in Beyond Wavelets, Academic Press, New York 2003.
[4]. Cunha et Al. The nonsubsampled contourlet transform:theory design and applications. IEEE Transactions on image Processing, 15(10), 2006, p.3089-3101.
[5]. Jignesh Sarvaiya, Suprava Patnaik & Hemant Goklani "Image Registration using NSCT and Invariant Moment" International Journal of Image Processing (IJIP), Volume (4): Issue (2) , May 2010,p.119-130.
[6]. Meskine, F.; Chikr el mezouar, M. and Taleb, N.." A Rigid Image Registration Based on the Nonsubsampled Contourlet Transform and Genetic Algorithm" , SENSORS, 10(9):. Sept.2010.,p 8553-8571.

Paper Type : Research Paper
Title : Test Data Compression Using Variable Prefix Run Length (VPRL) Code
Country : India
Authors : K.S.Ganesh kumar, Karen Thangam Jacob, B.Manjurathi
: 10.9790/4200-04219195    logo

ABSTRACT: One of the major challenges in testing a system-on-a-chip (SoC) is dealing with the large test data volume and large scan power consumption. To reduce the volume of test data, several test data compression techniques have been proposed. This paper presents a new test data compression scheme, which reduces test data volume for a system-on-a-chip (SoC). The proposed approach is based on the use of MT (Minimum Transition)-fill technique and Variable Prefix Run Length (VPRL) codes for test data compression. These VPRL codes can efficiently compress the data streams, that are composed of both runs of 0s and 1s. Experimental results for ISCAS'89 benchmark circuits supports and proves the proposed approach, better to the other existing techniques, by reducing test data volume.

Keywords: System on a chip, MT-Fill, AVR code, Test data compression, Compression ratio.

[1] J. Lee, N.A Touba, LFSR-reseeding scheme achieving low-power dissipation during test, IEEE Trans. On Computer-Aided Des. Integr. Circuits and System, Vol. 26, no. 2, 2007, pp. 396-401.
[2] Bo Ye, Qian Zhao, Duo Zhou, Xiaohua Wang, Min Luo, Test data compression using alternating variable run-length code, Elsevier, Integration, the VLSI journal, Vol.44, 2011, pp. 103-110.
[3] A. Chandra, K. Chakrabarty, System-on-a-chip Test Data Compression and Decompression Architecture based on Golomb Codes, IEEE Trans. On Computer-Aided Des. Integr. Circuits and System, Vol. 20, no. 3, 2001, pp. 355-368.
[4] A. Chandra, K.Chakrabarty, Test Data Compression and Test Resource Partitioning for System-oc-a-Chip using Frequency-Directed Run-length (FDR) Codes, IEEE Trans. Computers, Vol. 52, no. 8, Aug. 2003, pp. 1076-1088.
[5] A. H. El-Maleh, Test Data Compression for System-on-a-chip using Extended Frequency-Directed Run-Length Code, IET Computer digital Tech., Vol.2, no.3, 2008, pp. 155-163.
[6] M. Y. Wan, Y. Ding, Y. Pan, S. Zhou, X. L. Yan, Test Data Compression using Extended Frequency-Directed Run Length Code based on Compatibility, Electronics letters, Vol. 46, no. 6, Mar 2010, pp. 404-405.

Paper Type : Research Paper
Title : Implementation of Circuit Optimization Technique for Digital CMOS Comparator Using Parallel Prefix Tree Architecture
Country : India
Authors : P. Ranjith, P. Shankar Bharathi
: 10.9790/4200-04219698    logo
ABSTRACT: The digital comparator using CMOS cells that adopts the parallel prefix tree architecture. This comparator begins from most significant bit towards bit-wise least significant bit when two compared bits are equal. Using circuit optimization technique it reduced by 642 transistors from total area of 768 and also maximum fan-in and fan-out drives of five and four respectively and 1.78mW dynamic power dissipation for 16-bit (N) with 7 CMOS gate delay. The tanner EDA tool simulation for 16-bit is realized using 0.18-μm CMOS process technology with minimum supply voltage of 2.45V.
[1] Saleh Abdel-Hafeez, Ann Gordon-Ross, and Behrooz Parhami, Life Fellow, IEEE, "Scalable Digital CMOS Comparator Using a Parallel Prefix Tree," IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 21, Issue 11, pp. 1989-1998, November 2013.
[2] Anjuli, Satyajit Anand, "High-Speed 64-Bit Binary Comparator using Three Different Logic Styles," International Journal of Scientific & Engineering Research, Vol. 4, Issue 5, pp. 1076-1081, May 2013. [3] Joo-Young Kim, and Hoi-Jun Yoo, "BCL for Compact Digital Comparator," IEEE Asian Solid-State Circuits Conference, pp. 59-62, November 2007.

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