IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Nov. - Dec. 2016 Vol 6 - Issue 6

Version 1 Version 2 Version 3

Paper Type : Research Paper
Title : Partition and Sessionid Based Compilation Approach to Improve Re-Compilation Time and Efficient Use of Resources in Industry Standard Tools
Country : India
Authors : Sachin Puranik

ABSTRACT: The Design and Verification of SoCs is complex process due to multi-million transistors and the complexity of the actual design. The paper describes partition based compilation approach tagged with sessionids which can be derived to any industry standard VLSI design simulation tools. Thus if this methodology if implemented can be used to significantly reduce the compile time and manage the resources efficiently during re-compilations

Keywords: Partition, Compile, VCS, IRUN, VLSI, Modelling, recompilation

[1]. Synopsys VCS user guide version.
[2]. http://users.ece.utexas.edu/~patt/10s.382N/handouts/vcs.pdf
[3]. System- on -chip basics Springer-"Embedded Software Design and Programming of Multiprocessor System-onChip", Embedded Systems, Springer Science+ Business Media


Paper Type : Research Paper
Title : Mathematical Principals and Modeling of EEG Signal Exploration
Country : Bangladesh
Authors : Mamunur Rashid || Bifta Sama Bari || Md. Golam Sadeque

ABSTRACT: The electroencephalographic signal is a resultant signal of the action potential of neuron in the brain which inspects the neural functions. The brain signal is so subtle that it cannot be analyzed without amplification and this amplified signal is electroencephalogram (EEG). Electroencephalography is non-invasive appliance which is used in observing brain activities and detection of different disorder relating to the human brain. There are several objections of EEG for instance small signal amplitude, synchronizations, artifacts, temporal variability of signal and its sensitivity to noise.

Keywords: Electroencephalogram, EEG,Brain signal, Time domain, Frequency domain

[1]. Zhang xizheng, Yin ling and Wang weixiong, Wavelet Time-frequency Analysis of Electro-encephalogram (EEG) Processing,International Journal of Advanced Computer Science and Application,Vol.1, No. 5, pp. 1-6, 2012.
[2]. M. Teplan, Fundamentals of EEG Measurement, Measurement Science Review, vol. 2, pp. 1–11, 2002.
[3]. Rangaraj M. Rangayyan,Biomedical signal analysis, a case-study approach (John Wiley& Sons, INC 2002).
[4]. Silvia C. and David B. EEG classification using generative independent component analysis(Neurocomputing, 69, pp.769-777, 2006).
[5]. Jalili, M.; Barzegaran, E.; Knyazeva, M.G., Synchronization of EEG: Bivariate and Multivariate Measures, Neural Systems and Rehabilitation Engineering, IEEE Transactions on , vol.22, no.2, pp.212-221, 2014.


Paper Type : Research Paper
Title : A New Architecture Design Implementation of Non- Redundant Radix-4 Signed Multiplier Using HDL
Country : India
Authors : D.Hinduja || N.Srikanth || Dr.B.Subrahmaneswara Rao || J.E.N.Abhilash

ABSTRACT: This paper briefly presents architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values (-1;0;+1;+2) or (-2;-1; 0;+1) is proposed leading to a multiplier design with less complex partial products implementation. To implement some proposed pre-encoded NR4SD multipliers, including the coefficients memory to prove that they are more area and power efficient than the conventional Modified Booth scheme. By this proposed design the performance increases upto25% by decreasing 30%area and power consumption. By this critical path delay also decreases with decrease in area and power consumption

Keywords: Multiplying circuits, Modified Booth encoding, Pre-Encoded multipliers, VLSI implementation

[1]. A. Amaricai, M. Vladutiu, and O. Boncalo, "Design issues and imple-mentations for floating-point divide-add fused," IEEE Trans. Circuits Syst. II–Exp. Briefs, vol. 57, no. 4, pp. 295–299, Apr. 2010.
[2]. E. E. Swartzlander and H. H. M. Saleh, "FFT implementation with fused floating-point operations," IEEE Trans. Comput., vol. 61, no. 2, 284–288, Feb. 2012.
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[4]. S. Nikolaidis, E. Karaolis, and E. D. Kyriakis-Bitzaros, "Estimation of signal transition activity in FIR filters implemented by a MAC archi-tecture," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 1, pp. 164–169, Jan. 2000.
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Paper Type : Research Paper
Title : Implementation of New Gate Level Architecture for Carry-Select Adder for better Performance
Country : India
Authors : N.Nimshi || J.E.N.Abhilash || Dr.B.Subrahmaneswara Rao

ABSTRACT: This paper presents the reduction of logic operations involved in conventional carry select adder (CSLA) and binary to excess -1 converter BEC-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. Here eliminated all the redundant logic operations present in the conventional CSLA, BEC- CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, depending on the initial carry the total operation decides the operation of two individual blocks which itself generates the two final sum's and carry individually

Keywords:Adder, CSLA (Carry Select Adder),Arithmetic unit,low-power design,BEC (binary to excess -1).

[1]. S.Manju and V. Sornagopal, "An efficient SQRT architecture of carry selectadder design by common Boolean logic," in Proc. VLSI ICEVENT, 2013,pp. 15.
[2]. M. Z. Rahman and L. Kleeman, "A delay matched approach for the design of asynchronous sequential circuits,"Dept. Comput. Syst.Technol., Univ. Malaya, Kuala Lumpur, Malaysia, Tech. Rep. 05042013,2013.
[3]. B. Ramkumar and H.M. Kittur, "Low-power and area-efficient carry-select adder," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2,pp. 371–375, Feb. 2012.
[4]. I.-C. Wey, C.-C. Ho, Y.-S. Lin, and C. C. Peng, "An area-efficient carryselect adder design by sharing the common Boolean logic term," in Proc.IMECS, 2012, pp. 1–4.
[5]. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs,2nd ed. New York, NY, USA: Oxford Univ. Press, 2010


Paper Type : Research Paper
Title : Fpga Based Implementation of Video Authentication using Sensor Pattern Noise
Country : Pune.
Authors : Urvi M. Mittal || Rohita P. Patil

ABSTRACT: Video authentication plays an important role in identifying camera spoofing attacks occurred. Video Authentication can be accomplished by different methods on various platforms. Sensor Pattern Noise (SPN) is used for identifying tempered video or source identification of the video. The source is either authentic or non-authentic is identified using Forward and Inverse wavelet transform such as DWT and IDWT for performing reliable operations on frames of video extracted. MLE and MMSE estimations are calculated for denoising of the frame and for extraction of PNU noise which is treated as the fingerprint. Extraction of PNU is the basis of identification. The system is implemented on ZYNQ Xc7Z020 (ZedBoard) ARM/FPGA SoC development board using Xilinx ISE as well as VIVADO software for designing in VHDL language. The hardware resource utilization is reduced by implementing modified filter bank for DWT and IDWT.

Keywords:Video authentication; Sensor Pattern Noise;DWT; Denoising;Hardware Resource

[1] Pandeet al.: "Hardware Architecture For Video Authentication Using Sensor Pattern Noise "in IEEE transactions on circuits and systems for video technology, vol. 24, no. 1, January2014.
[2] S. Chen, A. Pande, K. Zeng, and P. Mohapatra, "Video source identification in lossy wireless networks," in Proc. IEEE Int. Conf. Comput. Commun., Mini-Conf., pp. 215–219, Apr. 2013.
[3] X. Kang, Y. Li, Z. Qu, and J. Huang, "Enhancing source camera identification performance with a camera reference phase sensor pattern noise," IEEE Trans. Inf. Forensics Security,, vol. 7, no. 2, pp. 393–402, Apr. 2012.
[4] D. Hyun, C. Choi, and H. Lee, "Camcorder identification for heavily compressed low resolution videos," Comput. Sci. Convergence, pp. 695–701, 2012.
[5] A. Pande and J. Zambreno, "Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression," ACM Trans. Embedded Comput. Syst., vol. 11, no. 1, pp.6:1–6:26, Apr. 2012.


Paper Type : Research Paper
Title : Fast Processing Unit Design to Mulitplier Using Block Unit Counting
Country : India
Authors : N. Srinivas || Y. Rajasree R

ABSTRACT: Multipliers are considered to be the basic building unit of all-basic to complex design units. This design unit operates on two operands and generates a result after successive bit wise anding and oring operation. With higher-level logical operation, the anding and oring operation is defined by addition and bit multiplication. The two operands are buffered on a register and temporary registers are used to buffer the intermediate results for adding these results. For faster processing, this block unit is defined in multiple ways for achieving optimization. Among these approaches, the multiplied design using parallel processing is adaptively been used. However, the resource overhead in such design is very large resulting in high area coverage and power dissipation. To overcome the stated issue in this paper, a new design approach following block unit count operation is suggested. The logical overhead in such design is minimized with the approach of redundant bit count in blocks.

Keywords:Multiplier design, fast processing, parallel multiplier, block unit counting

[1] S. K. Mitra, Digital Signal Processing: A Computer Based Approach. Boston, MA: McGraw-Hill, 2006.
[2] S. R. Vangal, Y. V. Hoskote, N. Y. Borkar, and A. Alvandpour, "A 6.2- GFLOPs floating-point multiply accumulator with conditional normalization," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2314–2323, Oct. 2006.
[3] L.-H. Chen, O. T. C. Chen, T.-Y.Wang, and Y.-C.Ma, "A multiplication- accumulation computation unit with optimized compressors and minimized switching activities," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'05), May 2005, vol. 1, pp. 6118–6121.
[4] A. Fayed, W. Elgharbawy, and M. Bayoumi, "A data merging technique for high-speed low-power multiply accumulate units," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process. (ICASSP'04), May 2004, vol. 5, pp. 145–148. [5] Liu, D.N.; Fitz, M.P., "Low complexity linear MMSE detector with recursive update algorithm for iterativedetection-decoding MIMO OFDM system,IEEE Conference Publications 2006


Paper Type : Research Paper
Title : Efficient Image Segmentation using Curve let and Contour let Transform for Bio-Medical Applications
Country : India
Authors : Y.Hima Deepthy || G.Amjad Khan

ABSTRACT: The goal of image fusion is to integrate complementary info from multifocus information such the new pictures area unit additional appropriate for the aim of human beholding and computer-processing tasks like segmentation, feature extraction, and beholding. This paper presents a picture fusion theme that is predicated on the Curveletmodel (DCT). The curvelet transforms of the input pictures area unit fittingly combined, and therefore the new image is obtained by taking the inverse Curvelet remodel of the united rippling coefficients. Associate in Nursing area unita-based most choice rule and a consistency verification step are used for feature choice. The projected theme performs higher than the Transform strategies as a result of the compactness, directional property,

[1]. B. K. Shreyamsha Kumar, M. N. S. Swamy, and M. Omair Ahmad, "Multiresolution DCT decomposition for multifocus image fusion," in 2013 26th Annu. IEEE Can. Conf. Electrical and Computer Engineering (CCECE), 2013, IEEE.
[2]. D. EgfinNirmala, R. K. Vignesh, and V. Vaidehi, "Multimodal image fusion in visual sensor networks," in 2013 IEEE Int. Conf. Electronics, Computing and Communication Technologies (CONECCT), 2013, IEEE.
[3]. H. Li, B. S. Manjunath, and S. K. Mitra, "Multisensor image fusion using the wavelet transform," Graph. Models Image Process., vol. 57.3, pp. 235–245, 1995.
[4]. O. Rockinger, "Image sequence fusion using a shift-invariant wavelet transform," in 1997 Proc. Int. Conf. Image Processing, 1997, vol. 3, IEEE.
[5]. Q. Zhang and B.-L. Guo, "Multifocus image fusion using the nonsubsampledcontourlet transform," Signal Process., vol. 89.7, pp. 1334–1346, 2009.


Paper Type : Research Paper
Title : Comparative Study on Image Denoising and Inpainting Techniques
Country : Bangladesh
Authors : Md Rifat Rayhan || M. S. Hossain || Nahyan Al Mahmud

ABSTRACT: Observed image signals are often corrupted by acquisition channel or artificial editing. The goal of image restoration techniques is to restore the original image from a noisy observation of it. Image denoising and inpainting are common image restoration problems that are both useful by themselves and important preprocessing steps of many other applications. Digital images are represented as matrices of equally spaced pixels, each containing a photon count. Due to the nature of light and environment it's natural that all images are noisy. Ever since digital images have existed, numerical methods have been proposed to improve the quality by reducing noise interference...............

Keywords: Denoising, Filtering, Inpainting, Restoration, Partial Differential Equations (PDEs), Gaussian noise, Salt and pepper noise

[1] Marcelo Bertalmío "Strong-Continuation, Contrast-Invariant Inpainting With a Third-Order Optimal PDE" IEEE TRANSACTIONS ON IMAGE PROCESSING, VOL. 15, NO. 7, JULY 2006
[2] "NASA Beams Mona Lisa to Lunar Reconnaissance Orbiter at the Moon"January17,2013 http://www.nasa.gov/mission_pages/LRO/news/monalisa.html#.VvpsVNJ97IU
[3] Rafael C. Gonzalez,Richard E. Woods,StevenL. Eddins "Digital Image Processing 2nd edition"
[4] Nachtegael, M, Schulte, S, Vander Weken. Kerre, "E.E.2005.Fuzzy Filters for Noise Reduction: The Case of Gaussian Noise". IEEE Xplore, 201-206 D, De Witte. V, 206.
[5] Mr. Salem Saleh Al-amri and et al. Comparative Study of Removal Noise from Remote Sensing Image. IJCSI International Journal of Computer Science Issues, Vol. 7, Issue. 1, No. 1, January 2010 32 ISSN (Online): 1694-0784 ISSN (Print): 1694-0814


Paper Type : Research Paper
Title : Design of Low Power Efficient CMOS Dynamic Latch Comparator
Country : India
Authors : A.Pravin || Dr.N.S.Murti Sarma || Dr.Fazal Noor Basha || Dr.M.Satyanarayana

ABSTRACT: High performance analog to digital converters (ADC), memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators.SAR-ADC is best suited for low power applications where power has a trade-off with speed.Comparator is one of the core components of SAR-ADC that introduces error voltage due to mismatch and consumes large power................

Keywords: Analog to digital converters (ADC), CMOS, Dynamic latch comparator, memory sense amplifiers, Radio frequency identification

[1] Heung Jun Jeon and Yong-Bin Kim, "A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator", Analog IntegratedCircuits and Signal Processing, vol. 70, no.3, pp. 337-346, March 2012.
[2] Pelgrom, M. J. M., Duinmaijer, A. C. J., &Weblbers, A. P. G. (1995), "Matchinproperties of MOS transistors", IEEE Journal of Solid- State Circuits, 24(10), 1433–1439.
[3] He, J., Sanyi, Z., Chen, D., & Geiger, R. L. (2009), "Analysis of staticanddynamicrandomoffsetvoltagesindynamiccomparators", IEEE Transactions on Circuits and Systems I: Regular Papers, 56, 911–919.
[4] Nikoozadeh,A,&Murmann, B. (2006), "An analysis of latch comparator offset due to load capacitor mismatch", IEEE Transactions on Circuits and Systems Part II: Express Briefs, 53(12), 1398–1402.
[5] Miyahara, M., et al. (2009),"A low-offset latched comparator using zero-static power dynamic offset cancellation technique", In IEEE A-SSCC, Taiwan, pp. 233–236.


Paper Type : Research Paper
Title : Adaptive Histogram Adjustment and DWT Based on Low-Resolution Satellite Data
Country : India
Authors : Suresh Akepogu || Dr. S Nagaraja Rao

ABSTRACT: In this paper a classy approach of image enhancement is proposed. This means combines two indeed popular techniques of enhancement, Wavelet corrosion and Adaptive histogram Equalization. Resolution and simplicity are the two having to do with attributes of an image. One of the roughly important how things stack up factors in images comes from its resolution. The enhancement is done both mutually respect to sentence and contrast. The about to be move uses DWT and SVD. The simplicity enhancement technique by SVD approach on peaceful frequency replace band of both input and Adaptive histogram Equalization images. The DWT technique decomposes the input theory into the four frequency replace bands and estimates the singular figure matrix of the low–low replace band brain wave, and, previously.......

Keywords: Low Resolution Satellite images, Adaptive histogram Equalization, Discrete wavelet transform (DWT), Singular value decomposition (SVD), Stationary wavelet transform (SWT), Inverse Discrete wavelet transform (IDWT), Mean Square Error(MSE) and Peak Signal to Noise Ratio(PSNR).

[1] Vasileios Syrris, Stefano Ferri, Daniele Ehrlich, and Martino Pesaresi," Image Enhancement and Feature Extraction Based on Low-Resolution Satellite Data"IEEE Journal Of Selected Topics In Applied Earth Observations And Remote Sensing, Vol. 8, No. 5, May 2015
[2] H. Demirel, C. Ozcinar, and G. Anbarjafari, ―Satellite image contrast enhancement using discrete wavelet transform and singular value decomposition,‖ IEEE Geosci. Remote Sens. Lett., vol. 7, no. 2, pp. 333–337,Apr. 2010.
[3] G. Srilekha, V. K. Kumar, and B. Jyothi, ―Satellite image resolutionenhancement using DWT and contrast enhancement using SVD,‖ Int. J.Eng. Res. Technol. (IJERT), vol. 2, no. 5, pp. 1227–1230, May 2013.
[4] Hasan Demirel and Gholamreza Anbarjafari, ―IMAGE Resolution Enhancement by Using Discrete and Stationary Wavelet Decomposition‖ IEEE transactions on IMAGE PROCESSING,VOL. 20, NO.5.
[5] H. Demirel and G. Anbarjafari, ―Satellite image resolution enhancement using complex wavelet transform,‖ IEEE Geosciences and Remote SensingLetter, vol. 7, no. 1, pp. 123–126, Jan. 2010.


Paper Type : Research Paper
Title : Selective Mapping and Partial Transmit Sequence Based PAPR Reduction for OFDM Applications
Country : India
Authors : Shailly Kumari || Dr. Rajesh Mehra

ABSTRACT: Although orthogonal frequency division multiplexing (OFDM) has many advantages but still it suffers high PAPR which is considered as its major drawback. To overcome this problem an amplifier with high dynamic range can be used but it will cause high cost to the system. In this paper two existing techniques are applied to decrease the peak to average power (PAPR) in orthogonal frequency division multiplexing (OFDM) system. These two techniques are selective mapping (SLM) and partial transmit sequence (PTS). Firstly, these two basic techniques are analysed and then SLM technique is modified with the use of Riemann matrix to optimize the phase sequence for.......

Keywords: LOrthogonal frequency division multiplexing (OFDM), Peak to average power (PAPR), Partial transmit sequence (PTS), Riemann-selective mapping (SLM), Selective mapping (SLM).

[1]. Samuel Oru, Besong, Xiaoyou Yu and Xiaochun Wang," A Hybrid PAPR Reduction Technique using FFT/IFFT based Tone Reservation and SLM with no Side Information", IEEE International Conference on Multimedia and Signal Processing, pp. 353-356, 2011
[2]. Kamal Singh, Manoranjan Rai Bharti and Sudhanshu Jamwal. "A modified PAPR reduction scheme based on SLM and PTS Techniques",IEEE International Conference on Signal Processing Computing and Control, pp.1-6, 15-17 March 2012.
[3]. J Armstrong, Orthogonal frequency division multiplexing: From Copper and Wireless to Optical, journal of Lightwave technology, vol. 27, pp. 189-204, 2009.
[4]. Stephen P. DelMarco, "General Closed-Form Family of Companders for PAPR Reduction in OFDM Signals Using Amplitude Distribution Modification", IEEE Transactions on Broadcasting, Vol. 60, No. 1, March 2014.
[5]. R. O'Neill and L. B. Lopes, "Envelope Variations and Spectral Splatter in Clipped Multicarrier Signals," Processing IEEE Personal indoor and mobile radio communication, Toronto, Canada, pp.71–75, Sept. 1995


Paper Type : Research Paper
Title : A Review on Sub-word unit Modeling in Automatic Speech Recognition
Country : India
Authors : Karpagavalli S || Chandra E

ABSTRACT: The primary issue in designing a speech recognition system is the choice of suitable modeling unit. Speech recognition systems may be based on any one of the modeling unit like, word, phoneme and syllable. The selection of sub-word unit depends on many factors such as vocabulary size, complexity of the task, language. Phoneme is the most commonly used sub-word unit in state-of-the-art speech recognition systems, which is an indivisible unit of sound of a particular language.......

Keywords: Sub-word unit, Phoneme, Syllable, Tri-phone, Acoustic segment, Speech recognition

[1]. Li Deng, Xiao Li, Machine Learning Paradigms for Speech Recognition: An Overview, IEEE Transactions on Audio, Speech, and Language Processing, 21(5), 2013, 1060-1089.
[2]. Jinyu Li, Li Deng, Reinhold Haeb-Umbach, Yifan Gong, ―Robust Automatic Speech Recognition: A Bridge to Practical Applications‖, Academic Press, 2015.
[3]. L. R. Rabiner, B. H. Juang, B. Yegnanarayana, ―Fundamental of Speech Recognition‖, Pearson Education Inc., New Delhi, India, 2009
[4]. K. Livescu, E. Fosler-Lussier, F. Metze, ―Sub-word modeling for automatic speech recognition: Past, present, and emerging approaches‖, IEEE Signal Processing Magazine, vol. 29, no. 6, pp. 44–57, 2012
[5]. B. H. Repp,―On levels of description in speech research‖, The Journal of the Acoustical Society of America, vol. 69, no. 5, pp.1462–1464, 1981.


Paper Type : Research Paper
Title : Low Power 2-D Mesh Network-on-Chip Router using Clock Gating Techniques
Country : India
Authors : Vijaykumar R Urkude || Dr. P. Sudhakara Rao

ABSTRACT: Network-on-Chip (NoC) is the platform of interconnection platform and is requirements of the modern on-Chip design. Area overhead, power consumption, and NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. An area efficient routing node for a NoC is presented in this paper. Out of the four components of routing node, the input block (mainly consisting of buffers) and scheduler have been modified to save area requirements. The other two components of the routing node take up negligible area in comparison. Custom SRAM is used in place of synthesizable flip flops in the input block........

Keywords: Clock Gating, Network-on-Chip, Router, RTL, SRAM,

[1] K. Latif, T. Seceleanu and H. Tenhunen, "Power and Area Efficient Design of Network-on-Chip Router through Utilization of Ideal Buffer", Proc.17th IEEE International Conference and workshop on Engineering of Computer based System, (2010).
[2] L. Benini and G. De Micheli, "Networks on Chips, Morgan", Kaufmann Publishers, (2006).
[3] W. Hangsheng, L. S. Peh and S. Malik, "Power- driven design of router micro architectures in on-chip networks", Proc. of the 36th Annual IEEE/ACM International Symposium on Micro architecture (MI-CRO), (2003), pp. 105-116.
[4] X. Chen and L. S. Peh, "Leakage power modeling and optimization of interconnection networks", Proc. of International Symposium on Low Power Electronics and Design, (2003), pp. 90-95.
[5] N. Banerjee, P. Vellanki and K. S. Chatha, "A Power and Performance Model for Network-on-Chip Architectures", Proc. of the conference on Design, automation and test in Europe (DATE), vol. 2, (2004), pp. 1250-1255.



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