iosr-JVSP   Volume-13 ~ Issue-3 ~ May - June 2023

ABSTRACT: Background: The increase in morbidity and mortality rates has made lung diseases a significant global public health concern. The emergence of the COVID-19 pandemic in late 2019 has brought even greater urgency for early and accurate diagnosis and management of these diseases. Chest X-rays are vital in identifying and monitoring lung diseases; however, accurate interpretation is challenging, time-consuming for large datasets, and prone to human error—particularly when detecting subtle signs or early stages of the diseases.
Materials and Methods: This paper presents a deep-learning-based CNN algorithm that utilizes transfer learning: to develop an automated AI tool capable of independently identifying various abnormalities and detecting diverse lung diseases.....

Keywords: Convolution Neural Network (CNN), Chest X-Ray (CXR) Imaging, Deep-learning (DL), Densely Connected Convolutional Network (DenseNet), Lung Diseases.

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ABSTRACT: Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down.This paper is about to compare the electrical performance of partially depleted (PD)SOI MOSFET at various gate oxide thickness.The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate oxide thickness, the leakage current and on-state current is increased but the threshold voltage is decreased and the sub-threshold slope is improved. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.

Keywords: MOSFET, Silicon on Insulator, Subthreshold Slope, Leakage Current, Threshold Voltage

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ABSTRACT: This work describes a design process, simulation, and analysis of a CMOS-based common source amplifier circuit in the Cadence Virtuoso environment at the 45 nm technology node. The suggested CMOS circuit may be useful in the op-amplifier or other circuits. The circuit is designed to work with a 1.8 V DC power source. The circuit is constructed from two complementary NMOS and PMOS transistors having a 45 nm gate length. The gate widths are chosen as 1 and 2 m, respectively. Transistors are selected from the gpdk045 library of the Cadence. For the simulation purpose, we have used.....

Keywords: CMOS; Common Source Amplifier; Cadence; Bandwidth; Gain; Technology Node; VLSI

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ABSTRACT: The main purpose of this paper is to compare three techniques to map directionality of polygonal fault systems (PFS) in Great South Basin (GSB), New Zealand. While the interpretation of polygonal to circular faults is often challenging, their identification is crucial in order to obtain detail subsurface condition. This study used 3D seismic-reflection analysis as a key tool to obtain fault geometry and directionality. The methods applied for polygonal faults mapping are Image J, manual interpretation and automated fault extraction. The time slices delineate the changes of PFS morphology through time. With the variance time slices, a preferred direction of the fault's structures can be computed by Image J directionality. The conventional method of fault interpretation such.....

Keywords: polygonal faults, orientation, planform geometry, variance, attribute, pockmarks

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