IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Mar - Apr. 2015 Vol 5 - Issue 2

Version 1 Version 2

Paper Type : Research Paper
Title : An Improved Speech De-noising Method based on Empirical Mode Decomposition
Country : India
Authors : Mr. S. Nageswara Rao || Dr. K. Jaya Sankar || Dr. C.D. Naidu

ABSTRACT: Generally, Speech enhancement aims to improve speech quality and intelligibility of a noise contaminated speech signal by using various signal processing approaches. Removal of a noise from a noisy speech is a common problem; already a vast research was carried out in earlier. However, due to the characteristics of various types of noises, the approaches proposed in earlier are not applicable for all types of noises. In addition, the earlier approaches didn't focus on the non-linear and non-stationary characteristics on noise environments. EMD is a filtering approach performs efficiently for non-stationary environments. This paper proposes a novel EMDF approach with the inspiration of thresholding to remove the noise from noisy speech sample. The proposed approach also developed a method to select the IMF index for separating the residual low-frequency noise components from the speech estimate, based on the IMF statistics. An experimental study was also done on various types of noise contaminated speech samples like babble noise, restaurant noise and car interior noise at various strengths.

Keywords: Speech enhancement, EMDF, IMF, noise estimation, SegSNR.

[1]. I. Cohen and B. Berdugo, "Speech enhancement for non-stationarynoise environments", in Signal Processing. Amsterdam, the Netherlands:Elsevier, Nov. 2001, vol. 81, pp. 2403–2418.
[2]. Sohn J. and Kim N, "Statistical Model based voice activity detection", IEEE Signal Processing Letters, Jan 1999, Volume:6 , Issue: 1 ) pp.1-3.
[3]. Shrinivasan K. and Gersho A. (1993), "Voice ActivityDetection for Cellular Network", Prec. IEEE Speech CodingWorkshop pp. 85-86.
[4]. R. Martin, "Noise PSD estimation based on optimal smoothing andminimum statistics," IEEE Trans. Speech Audio Process., vol. 9, no. 5,pp. 504–512, Jul. 2001.
[5]. I. Cohen, "Noise spectrum estimation in adverse environments: Improvedminima controlled recursive averaging," IEEE Trans. SpeechAudio Process., vol. 11, no. 5, pp. 466–475, Sep. 2003.
[6]. Tien Dung Tran, "Speech enhancement using modified IMCRA and OMLSA methods", Third International Conference on Communications and Electronics (ICCE), Aug. 2010.
[7]. Anuradha R. Fukane, Shashikant L. Sahare, "Noise estimation Algorithms for Speech Enhancement in highlynon-stationary Environments", IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 2, March 2011ISSN (Online): 1694-0814.

Paper Type : Research Paper
Title : HDL Implementation and Performance Comparison of an Optimized High Speed Multiplier
Country : India
Authors : Arati Sahu || Siba Kumar Panda || SwarnaPrabha Jena

ABSTRACT: This paper is devoted for the design of an optimized high speed Vedic multiplier using Udhava-Tiryakbhyam sutra. High speed multiplier is required to perform critical multiplication operation of Digital Signal processing applications like DFT,FFT, convolution , Arithmetic and logic unit(ALU) and Multiply and Accumulate(MAC). This paper shows the Multiplier architecture for 2×2, 4×4,8×8 and 16×16 .The performance has been evaluated in XILINX ISE 9.2.Synthesis and simulation have been performed for various architectures considering delay, number of slices, power and area.

Keywords: Vedic Mathematics, Vedic multiplier, Udhava- Tiryakbhyam, Array multiplier, Booth Algorithm, Digital Signal Processing, VLSI Signal processing, Verilog.

[1]. Rutuparna panda,M.pradhan," Speed comparision of 16*16 vedic multipliers" IJCA,vol-21,may-2011
[2]. M.Pradhan, R.Panda, S K Sahu, " MAC Implementation using Vedic Multiplication Algorithm," IJCA (0975-8887), Vol-21, No.7, may 2011.
[3]. M.Pradhan, R.Panda, "Design and Implementation of Vedic Multiplier," A.M.S.E. Journal, vol.15, Issue 2,pp.1-19, July 2010.
[4]. A Nanda, S Behera, "Design and Implementation of Urdhva-Tiryakbhyam Based 8×8 Vedic Binary Multiplier", IJERT, Vol.3,Issue 3, March 2014.
[5]. Poornima M, Shivaraj Kumar Patil, Shivukumar , Shridhar K P , Sanjay H, "Implementation of Multiplier using Vedic Algorithm", International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-2, Issue-6, May 2013.
[6]. Premananda B.S., Samarth S. Pai, Shashank B., Shashank S. Bhat "Design and Implementation of 8-Bit Vedic Multiplier " International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 12, December 2013.

Paper Type : Research Paper
Title : Performance Analysis of a 6T SRAM Cell in 180nm CMOS Technology
Country : India
Authors : Rohit Kumar Sah || Inamul Hussain || Manish Kumar

ABSTRACT: SRAM is a memory component and is used in various VLSI chips due to its unique capability to retain data. This memory cell has become a subject of research to meet the demands for future communication systems. In this paper a 6T SRAM cell is designed by using cadence virtuoso EDA tool in 180nm CMOS technology. Its performance characteristics such as power dissipation, delay, and power delay product are analysed. Power dissipation, delay, and power delay product of the designed 6T SRAM cell are 54.63 x10-9 W, 19.96 x10-9s, and 1070.45 x 10-18 Ws respectively.

Keywords: Power, Delay, Power delay product, 6T SRAM cell.

[1] P. Athe, and S. Dasgupta, A Comparative Study of 6T, 8T and 9T Decanano SRAM cell, IEEE Symposium on Industrial Electronics and Applications, 2, 2009, 889-894.
[2] R. K. Sah, I. Hussain, and M. Kumar, Performance Comparison for Different Configurations of SRAM Cells, International Journal of Innovative Research in Science, Engineering and Technology, 4, 2015, 18543-18546.
[3] N. Rahman, and B. P. Singh, Design of Low Power SRAM Memory Using 8T SRAM Cell, International Journal of Recent Technology and Engineering, 2, 2013, 123-127.
[4] A. Agal, Pardeep, and B. Krishan, 6T SRAM Cell: Design and Analysis, Journal of Engineering Research and Applications, 4, 2014, 574-577.
[5] D. Aggarwal, P. Kaushik, and N. Gujran, A Comparative Study of 6T, 8T and 9T SRAM Cell, International Journal of Latest Trends in Engineering and Technology, 1, 2012, 44-52.

Paper Type : Research Paper
Title : Performance Analysis Comparison of a Conventional Wallace Multiplier and a Reduced Complexity Wallace multiplier
Country : India
Authors : Inamul Hussain || Rohit Kumar Sah || Manish Kumar

ABSTRACT: In this paper performance analysis comparison of a conventional wallace multiplier and a reduced complexity wallace multiplier is presented. Performance comparison is done in terms of power, delay, power delay product and complexity in terms of number of MOS transistors. The multipliers are designed by using Cadence virtuoso in 180nm CMOS technology and their performance characteristics are analysed. Performance improvement of the designed 4x4 bit reduced complexity wallace multiplier with respect to the designed 4x4 bit conventional wallace multiplier in terms of number of transistors, delay and power delay product are found to be 12.05%, 9.42% and 4.98% respectively.

Keywords: Power, Delay, Power delay product, Reduced complexity, Conventional wallace multiplier, Reduced complexity wallace multiplier.

[1] C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Computers, 13, 1964,14-17.
[2] D. R. Gandhi, and N. N. Shah, Comparative Analysis for Hardware Circuit Architecture of Wallace Tree Multiplier, IEEE International Conference on Intelligent Systems and Signal Processing, Gujarat, 2013, 1-6.
[3] C. Vinoth, V. S. K. Bhaaskaran, B. Brindha, S. Sakthikumaran, V. Kavinilavu, B. Bhaskar, M. Kanagasabapathy, and B. Sharath, A Novel Low Power and High Speed Wallace Tree Multiplier for RISC Processor, IEEE 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, 330-334.
[4] Hussain, and M. Kumar, Design and Analysis of a Conventional Wallace Multiplier in 180nm CMOS Technology, IOSR Journal of VLSI and Signal Processing, 5, 2015, 60-65.
[5] E. E. Swartzlander, and R. S. Waters, A Reduced Complexity Wallace Multiplier Reduction, IEEE Transactions on Computers, 59, 2010, 1134-1137.

Paper Type : Research Paper
Title : Implementation Of Fuzzy Logic In Conveyor Belt
Country : India
Authors : Anu Varghese || Athira K. Raveendran || Divya Kuriakose || Manjula G.

ABSTRACT: Conveyorbeltsaremainlyusedinairports, industriesandvarioussecurityschemes.Itsmainpurposeis tocarrythegoods. In modernworld theusageofconveyorbelt increases in differentways. Notonlyused inindustriesbutalsointhehotels.Forsecuritychecking,trackingandscanningofgoodsareemployed in variousstations. Implementation oftheFuzzylogic techniques forLocalizationandtrackingof itemsmovingalongaconveyorbeltcanbedeterminedbyrulebaseddecisionmaking.UHF-RFID modulesareused for the localization ofitems. The traditionalBooleansettheoryhelps to introduce fuzzy concept in this paper. Threedimensionalviewsof theitems havebeen determinedhere. Foreasyand quick implementationFuzzycontrollercanbedefinedbyprocesscontrol.RFID modulesprovide two dimensionalviews ofitemand RFIDreadersketchtheitemfromconveyorbelt

Keywords-FuzzyLogic,Rulebaseddecisionmakingtheory,UHF-RFID(UltraHigh Frequency-RadioFrequency Identification).

[1]. AkshayAthalye,VladimirSavi´c,MiodragBoli´c,andPetarM.Djuri´c(2013),"NovelSemi-PassiveRFID SystemforIndoorLocalization"IEEESENSORSJOURNAL,VOL.13,NO.2.
[2]. EmidioDiGiampaolo andFrancescoMartinelli,(2012)"APassiveUHF-RFIDSystemfortheLocalization ofan
[3]. Fang-HuaXing,(2011)"EmbeddedIntelligentSensorforConveyerBeltFuzzySystem Application"International
[4]. LukeMirowskiandJackyHartnett(2007),"Deckard:ASystemtoDetectChangeofRFIDTagOwnership"
[5]. MartinScherhäufl,MarkusPichlerandAndreasStelzer(2014), "UHFRFIDLocalizationBasedonPhase
[6]. PavelV.NikitinandK.V.S.Rao(2008)"AntennasandPropagationinUHFRFIDSystems"IEEERFID2008conferenceproceedings.

Paper Type : Research Paper
Title : Design of Ultra Wideband Low Noise Amplifier with the Negative Feedback using Micro strip Line Technique
Country : India
Authors : Bhushan R. Vidhale || Dipali C . Nitnaware || Dr.M.M.Khanapurkar

ABSTRACT: In this, a Design of Ultra Wideband Low Noise Amplifier with the Negative Feedback using Micro strip Line Technique is discussed. LNA design is a crucial thing and challenging task at the receiver since received signal will always be weaker in amplitude and corrupted by noise in wireless communications. It should provide low noise figure not only at one frequency but over range of frequencies or bandwidth of interest. Also requirements of minimum noise figure and maximum gain will always be design trade-offs and can't be met simultaneously. We need an optimization and fine tuning of component values to get the optimum results. In recent years, as mobile communication, satellite communications, microwave test equipments etc call for small size, wideband, low noise and higher frequency band, lower noise and wider bandwidth design of microwave transistor amplifiers is more highly demanded. Compared to traditional narrow-band LNA, design of ultra wide-band LNA is quite different and provides much more challenges, such as broad-band input matching to minimize the return loss, sufficient and flat gain, low noise figure (NF), low power consumption and good linearity .To achieve its wide-band characteristics, the negative feedback is adopted using a matching mechanism, which consists of lumped elements and micro-strip lines. The software ADS is used to optimize design and the whole matching network.

Keywords: Ultra wideband, Low noise amplifier (LNA), Negative feedback, Micro strip lines..

[1]. Design of wideband high gain and low noise amplifierYinhua Yao and Tongxiu Fan.
[2]. Design of DC-3.4GHz Ultra-Wideband Low Noise Amplifier with Parasitic Parameters of FET Yinhua Yao*, Tongxiu Fan.
[3]. D. Barras, F. Ellinger, and H. Jackel, "A comparison between ultrawideband and narrow-band transceivers," TRLabs/IEEE Wireless 2002, pp. 211–214, Jul. 2002.
[4]. Rowan Gilmore, Les Besser, Practical RF Circuit Design For Modern Wireless Systems, vol. II: Active Circuits And Systems,2003, pp. 123- 141.
[5]. Kenington, P. B., High-Linearity RF Amplifier Design, Norwood, MA: Artech House, 2000.
[6]. C.W. Kim, M.-S. Kang, P. T. Anh, H.-T. Kim, and S.-G. Lee, "An ultra wide-band CMOS low-noise amplifier for 3–5-GHz UWB system,"IEEE J. Solid-State Circuits, vol. 40, pp. 544–547, Feb. 2005.

Paper Type : Research Paper
Title : The High performance Multiplexer based Adder Circuits
Country : India
Authors : Dr. K. Ragini

ABSTRACT: The need for extending low power circuits increased with the advent of use of large number of portable devices like cell phones, calculators, miniature computers etc. In all these devices, a long battery life is desired. An increase in battery life can be achieved by reducing power consumption of individual circuits. One of the methods to reduce the power consumption is by operating the devices at low current and low voltages. Operating the devices below threshold voltages is called as sub-threshold operation and the region of operation is called sub-threshold region. In this region, leakage current is used as operating current and power consumption is reduced significantly. The paper mainly focuses on the operation of various High performance Multiplexer based digital 1-bit Adder circuits[1] in sub-threshold region. The reduction in average power when compared to their super-threshold operation is analyzed. The variation of performance parameters and limitation of frequency of operation with variation in supply voltage are investigated. By varying the supply voltage below the threshold voltage, power can be reduced considerably. All the investigations in the paper are carried out using H-spice simulation tool. The circuits used are of 65nm process technology.

Keywords: Sub-threshold , Propagation delay , Adder, power delay product, Power dissipation.

[1] Abdulkarim Al-Sheraidah, Bassem Alhalabi, and Hung Tien Bui, "Five New High-Performance Multiplexer-Based 1-Bit Full Adder Cells", IEEE 2001.
[2] Anantha P.Chandrakasan, S.Sheng and R.W. Brodersen, "Low-Power CMOS Digital Design", IEEE journal of Solid State Circuits Vol.27, No.4, April 1992.
[3] H. T. Bui, A. K. Al-Sheraidah, and Y. Wang, "Design and Analysis of 10-transistor full adders using novel XOR-XNOR gates", IEEE transaction on Circuits And Systems, Vol.49, Issue:1, Jan 2002.
[4] James Kao, Siva Narendra, and Anantha Chandrakasan, "Sub-threshold leakage modelling and reduction techniques, IEEE, 2002.
[5] R. Shalem, E. John, L. K. John, "A Novel Low Power Energy recovery Full adder Cell", in Proc. Great Lakes Symp. VLSI, Feb. 1999.
[6] Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Shah, and Jin-Gyun Chung, "A Novel Multiplexer-Based Low-Power Full adder", IEEE Transactions on Circuits and Systems, Volume 51,No. 7, July 2004.

Paper Type : Research Paper
Title : GMM Classifier for Identification of Neurological Disordered Voices Using MFCC Features
Country : India
Authors : K. Uma Rani || Mallikarjun S Holi

ABSTRACT: Automatic detection of neurological disordered subjects voice mostly relies on parameters extracted from time-domain processing. The calculation of these parameters often requires prior pitch period estimation; which in turn depends heavily on the robustness of pitch detection algorithm. In the present work cepstral-domain processing technique which does not require pitch estimation has been adopted to extract the features of voice signal. The Mel frequency cepstral coefficients (MFCCs) are computed using two methods; the fast Fourier transform (FFT) and the linear predictive coding (LPC) method. The cepstral parameters estimated from these methods are used as features to classify normal subject voice from neurologically disordered subject's voice using Gaussian mixture model (GMM). The results of the two methods are compared, and it is found that the accuracy of LPC-MFCC based GMM classifier is 89.55% compared to FFT-MFCC based GMM classifier which is giving an accuracy of classification of 88.5%.

Keywords - Fast Fourier Transform, Gaussian mixture model, Linear prediction coefficient, Mel frequency cepstral coefficient.

[1] R.J.Baken, R.F.Orlikoff, Clinical measurement of speech and voice (2nd edition, singular Thomson learning, 2000).
[2] P. Henriquez, J. B. Alonso, M. A. Ferrer, C. M. Travieso, J. I. Godino-Llorente, and F. Diaz-de-Maria, Characterization of healthy and pathological voice through measures based on nonlinear dynamics, IEEE Trans. Audio, Speech, Lang. Process, vol., 17,no.6, 2009,1186–1195.
[3] Nicolas, Saenz-Lechon, Juan I. Godino-Llorente,Vıctor Osma-Ruiz , Pedro Gomez-Vilda Methodological issues in the development of automatic systems for voice pathology detection , J.of Biomed. Sig.Proc. and Cont., vol. 1, no.2, 2006, 120–128.
[4] Stefan Hadjitodorov, Petar Mitev, A Computer System For Acoustic Analysis Of Pathological Voices And Laryngeal Diseases Screening, J.of Med. Eng.Phy., vol. 24, no.6, 2002, 419-429.
[5] Paulo R. Scalassara, Carlos D. Maciel, And Jos_E C. Pereira Predictability Analysis Of Voice Signals, Analysing Healthy And Pathological Samples, Med. and Bio. Mag., vol.28, no.5, 2009,30-34.
[6] Juli A N David Arias-Londo N O , Juan I. Godino-Llorente , Maria Markaki & Yannis Stylianou, On combining information from modulation spectra and mel-frequency cepstral coefficients for automatic detection of pathological voices, J. of Logopedics Phoniatrics Vocology, vol.36, no.2,2011,60-69..

Paper Type : Research Paper
Title : Integrity and Confidentiality for Skypilot Port Communication
Country : India
Authors : Majel Monisha.B || Jose Anand

ABSTRACT: Wireless communication offers the benefits of low cost, rapid deployment, shared communication medium, and mobility, while at the same time has many security and privacy challenges. Dynamic Encryption Scheme, when used between two parties of communication, the former packets are coded as retransmission sequence, where as the retransmitted packet is marked as "1" and the other is marked as "0." During communication, the retransmission sequence is generated at both sides to update the dynamic encryption key. If retransmission sequence is missed or misjudged it would prevent the adversary from achieving the keys. The basic idea of dynamic secret is that the legitimate users dynamically generate a shared symmetric secret key utilizing the inevitable transmission errors and other random factors in wireless communication..

[1]. Komninos,E. Philippou and A. Pitsillides, Survey in Smart Grid and Smart Home Security: Issues, Challenges and Countermeasures, IEEE Communications Surveys & Tutorials,2013.
[2]. Filippo Gandino, Bartolomeo Montrucchio, and Maurizio Rebaudengo ,Key Management for Static Wireless Sensor Networks With Node Adding,IEEE Transactions On Industrial Informatics, Vol. 10, No. 2, May 2014, pp 1133 – 1143.
[3]. Jinguang Han, Willy Susilo, and Yi Mu, Identity-Based Secure Distributed Data Storage Schemes, IEEE Transactions On Computers, Vol. 63, No. 4, April 2014, pp 941 - 953.
[4]. Dai Wang, Xiaohong Guan, Ting Liu, Yun Gu, Yanan Sun, Yang Liu ,A Survey on Bad Data Injection Attack in Smart Grid, Ministry of Education Key Lab for Intelligent Networks and Network Security, School of Electronic and Information Engineering, Xi‟an Jiaotong University, Xi‟an, Shaanxi, China, IEEE 2013.
[5]. Anthony R. Metke and Randy L. Ekl, Security Technology for Smart Grid Networks, IEEE Transactions On Smart Grid, Vol. 1, No. 1, June 2010, pp 99 – 107.
[6]. Reza Soosahabi, Mort Naraghi-Pour,Dmitri Perkins, and Magd A Bayoumi,Optimal Probabilistic Encryption for Secure Detection in Wireless Sensor Network,IEEE Transactions On Information Forensics And Security, Vol. 9, No. 3, March 2014, pp 375 – 384.

Paper Type : Research Paper
Title : Power Reduction in CMOS Sub-threshold Dual Mode logic circuits by Power Gating
Country : India
Authors : Celine Elsa Jose || B Kousalya

ABSTRACT: Power dissipation has always been a major concern in integrated circuit design. Even during static state, there is a small amount of leakage power. In this project we have implemented various Power gating techniques like Sleep, Dual Sleep and Sleepy Stack in Sub threshold Dual mode logic circuits. This logic can bring down the total power. Hence a comparative analysis of power consumption is performed. The Dual mode logic has two modes of operation namely Static and Dynamic. In Static mode, there is a considerable decrease in the power consumed along with a moderate performance. Dynamic mode renders high performance compromising on an increase in power consumption. Power gating employs sleep transistors to isolate the circuit thereby reducing leakage power. The power is evaluated using Tanner Simulation tool under 180nm technology.

Keywords: Complementary MOS, Dual Mode Logic (DML), static power

[1]. Asaf Kaizerman, Sagi Fisher, and Alexander Fish, "Subthreshold Dual Mode Logic," Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 21, No. 5, MAY 2013
[2]. M. Alioto, "Ultralow power VLSI circuit design demystified and explained: A tutorial," IEEE Trans. Circuits Syst. I, vol. 59, no. 1, pp.3–29, Jan. 2012.
[3]. A.P.Chandrakasan, S.Sheng and R.W.Brodersen, "Low-power CMOS digital, "Solid-State Circuits, IEEE Journal of, vol.27, pp.473-484, 2002.
[4]. D.Bol, R. Ambroise, D. Flandre, and J. D. Legat, "Analysis and minimization of practical energy in 45 nm subthreshold logic circuits," in Proc. IEEE Int. Conf. Comput. Design, Oct. 2008, pp. 294–300.
[5]. N,Verma, J. Kwong and A.P. Chandrakasan, "Nanometer MOSFET variation in minimum energy subthreshold circuits," IEEE Transactions on Electron Devices, vol. 55, pp. 163-174, 2008.
[6]. J. Kao, S. Narendra and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," in Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 141-148, 2002.

Researcher can also search IOSR published article contents through

IOSR Xplore