IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

May - Jun. 2015 Vol 5 - Issue 3

Version 1 Version 2

Paper Type : Research Paper
Title : A Modern Approach for Low Power Dynamic Double Tail Comparator
Country : India
Authors : A.Muthumanicckam || R.Sornalatha || L.Vijayprabakaran

ABSTRACT: Dynamic comparators are widely used in the design of high speed analog to digital converters (ADCs).Clocked comparators are often called dynamic comparators. Dynamic double tail comparators are compared in terms of their power, speed and delay. The accuracy of comparators, which is defined by its power consumption and speed, is of keen interest in achieving over all higher performance of ADCs. In the domain of signal processing with low power VLSI, the role of ADC system is essential. Many high speed ADCs, such as flash ADCs, require high speed, low power comparators with small chip area. The dynamic comparator is based on bipolar CMOS technology. This is the combination of Bipolar and CMOS technology. The Bipolar CMOS circuit offers high speed, high gain and low output resistance, which are excellent properties for high-frequency analog amplifiers and CMOS technology offers high input resistance and is excellent for constructing simple, low-power logic gates.

Keywords- ADC (Analog to Digital converter), CMOS (Complementary Metal Oxide Semiconductor), Flash ADC, Dynamic double tail comparator, Bipolar CMOS.

[1]. S. Babayan-Mashhadi and R.Lotfi, "An offset cancellation technique for comparators using body-voltage trimming," Int. J. Analog Integr .Circuits Signal Process., vol. 73, no. 3, pp. 673–682, Dec. 2012.
[2]. S. U. Ay, "A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,"Int. J. Analog Integr. Circuits Signal Process., vol. 66,no. 2, pp. 213–221, Feb. 2011.
[3]. A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, "Supplyboosting technique for designing very low-voltage mixed-signal circuits in standard CMOS," in Proc. IEEE Int. Midwest Symp. Circuits Syst.Dig. Tech. Papers, Aug. 2010, pp. 893–896.
[4]. J. Kim, B. S. Leibowits, J. Ren, and C. J. Madden, "Simulation and analysis of random decision errors in clocked comparators,"IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1844–1857, Aug. 2009.
[5]. J. He, S. Zhan, D. Chen, and R. J. Geiger, "Analyses of static and dynamic random offset voltages in dynamic comparators,"IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 911–919, May 2009.

Paper Type : Research Paper
Title : Comparative Analysis of Multiplier in Quaternary logic
Country : India
Authors : Shweta Hajare || Dr.P.K.Dakhole

ABSTRACT: Multiple Valued Logic (MVL) has some important benefits such as increased data density, increased computational ability, reduced dynamic power dissipation Therefore with the help of Multiple Valued Logic (MVL) we have designed two quaternary multiplier architecture. The partial products in the multiplier are designed with quaternary voltage mode circuits. Each multiplier architecture is designed with two methods. The performance of two quaternary multiplier architecture is then compared based on Energy delay product (EDP) & Power delay product (PDP) . Comparison of these multiplier is done based on the analysis for power delay & area

Keywords - Multiple Valued Logic (MVL) , Quaternary logic, NMIN, NMAX.

[1]. Y K Yamanaka, T Nishidha, T Saito, M Shimohigashi, and K Shimizu, A. Hitachi Ltd., Tokyo " A 3.8-ns CMOS 16x16-bit multiplier using complementary pass-transistor logic," IEEE Journal of Solid-State Circuits, vo1.25, no 2,pp.388-95, 1990
[2]. K. C. Smith, "Multiple-valued logic: a tutorial and appreciation," IEEE Computer, vol.21, pp. 17–27,Apr. 1988
[3]. Ricardo Cunha, Henri Boudinov and Luigi Carro "Quaternary Look-up Tables Using Voltage-Mode CMOS Logic Design"Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)pp.56-56, 2007, 13-16 May, 2007.
[4]. Ricardo Cunha G. da Silva , "A Novel Voltage Mode CMOS Quaternary Logic Design" , IEEE Transactions on Electron Devices , vol.53, no. 6 , June 2006.
[5]. Satyendra R.P.Raju Datla, Mitchell A. Thornton "Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits*" ISMVL.2010
[6]. J.T. Butler, (editor), Multiple-Valued Logic in VLSI Design, IEEE Computer Society Press, 1991

Paper Type : Research Paper
Title : Quadrature Delta Sigma Modulator Design and Overview
Country : India
Authors : Samiksha Yadav || Bhargav Panchal || Gaurav Dhiman

ABSTRACT: Quadrature Band pass ADC is well known to be adopted in order to reduce the system complexity, increase integration and improve performance by digitizing the bandpass signal directly without prior conversion to baseband. The Quadrature sigma delta modulator is analyzed for different quantization level for the different parameters like Signal to noise distortion ratio, quantization noise rejection capability for various devices. The result highlights the analysis of different quadrature bandpass modulators which provides a good order modulator and help to enhance device efficiency.

Keywords: Analog-to-digital conversion, bandpass delta-sigma modulator, Signal to Noise Ratio, Quantization Noise

[1]. A. Maxim, R. Poorfard, and M. Chennam, "0.13μm cmos dbs demodulator front-end using a 250ms/s 8 bit time interleaved pipeline adc and a sampled loop filter pll," Radio and Wireless Symposium
[2]. (RWS), pp. 53 – 56, January 2008
[3]. P.-I. Mak, K.-K. Ma, W. leng Mok, C. sam Sou, K. man Ho, C.-M. Ng, S.-P. U, and R. Martins, "An i/q-multiplexed and ota-shared cmos pipelined adc with an a-dqs s/h front-end for two-step-channel-select low-if receiver," Proc. of Circuits and
[4]. Systems (ISCAS), vol. 1, pp. I– 1068–I–1071, May 2004
[5]. S. A. Jantzi, K. W. Martin, and A. S. Sedra,
[6]. "Quadrature bandpass modulation for digital radio," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1935 – 1950, December 1997
[7]. R. Schreier, N. Abaskharoun, H. Shibata, D.

Paper Type : Research Paper
Title : VLSI Based Vehicle Security and Accident Information System
Country : India
Authors : Tejvir Singh Chhikara || Ankit

ABSTRACT:VLSI based vehicle security and accident information system is useful to avoid the accidents and to provide vehicle security against theft. Security of the vehicle is done by password. Theft information is sent to owner's mobile by using GSM module. Accident of the vehicle is detected by using pressure sensor which is connected in the vehicle. The information of accident is sent to the hospital which is nearby for the location point of view. The location of the vehicle is identified with help of most famous technique called GPS technique. So almost this work is based on VLSI. As there are different module which are used for security and accident information. In order to make the combined system that performs the purpose of vehicle security and accident information system can be achieved by interfacing. For this interfacing these modules FPGA will be used.
Keywords: Very large scale integration, Global system for mobile communication, Global positioning system and Field programmable gate array.

[1]. Trimberger, S., 1994. Ed., Field-Programmable Gate the accident spot, as soon as possible. Array Technology, Kluwer, Academic Publishers.
[2]. Oldfield, J. and R. Dorf, 1995. Field Programmable there is none in the car. Gate Arrays, John Wiley & Sons, New York
[3]. Rose, J., A. El Gamal and A. Sangiovanni-Vincentelli, 1993. Architecture of Field-Programmable Gate Arrays, in Proceedings of the IEEE, 81(7): 1013-1029.

Paper Type : Research Paper
Title : Simulation of Propagation Delay of Multi and Single Conductor MLGNR in Nano Scale Region
Country : India
Authors : Praggya Agnihotry || R.P.Agarwal

ABSTRACT:The paper deals with the analysis of propagation delay of multi-layer graphene nano-ribbon (MLGNR) using single and multi conductor equivalent models at 16 nm for driver-interconnect-load (DIL) system. The length of MLGNR varies from 100 μm to 1000 μm has been used for GNR at different layers 3, 10 and 20. Three threshold voltages 0.5V (super threshold region), 0.3V (near threshold region), and 0.2V (sub threshold region) have been used for different number of devices connected in parallel.

Keywords: CMOS, Driver-Interconnect-Load (DIL), FinFET, Multi conductor equivalent model, Single conductor equivalent model. array.

[1]. A. Naeemi and J. D. Meindl, Conductance modeling for grapheme nanoribbon (GNR) interconnects, IEEE Electron Device Lett., vol. 28,no. 5, 2007, pp. 428–431.
[2]. A. Naeemi and J. D. Meindl, Performance benchmarking for graphene nanoribbon, carbon nanotube, and Cu interconnects, in Proc. IEEE Int. Interconnect Technol. Conf., San Francisco, CA, 2008, pp. 183–185.
[3]. C. Xu, H, Li, and K. Banerjee, Modeling, analysis, and design of graphene nano-ribbon interconnects, IEEE Trans. Electron Devices, vol. 56, no. 8, pp, 2008, 1567-1578,
[4]. T. Ragheb and Y. Massoud, On the Modeling of Resistance in Graphene Nanoribbon (GNR) for Future Interconnect Applications, in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD 2008), 2008, pp.593-597.
[5]. Y. Fang, W. Zhao, X. Wang, F. Jiang, and W. Yin, Circuit modelling of multilayer graphene nanoribbon (MLGNR) interconnect, in IEEE Conference (APEMC), 2012 Asia-Pacific Symposium, 2012, pp. 625 – 628.

Paper Type : Research Paper
Title : Design and Implementation of Low power Carry Select Adder Using Transmission Gate Logic
Country : India
Authors : Chandan Kumar Ray || K.Srinivasarao

ABSTRACT: Now A days power Reduction techniques play important Role in Low power VLSI Applications. Adder is digital circuit it performing addition operation used in many application like microprocessor and DSP In this paper Low power XOR gate has been designed using transmission gate logic, it is implemented carry select adder for low power VLSI application and compared with CMOS technology . The simulation is performed using a SPICE circuit simulator at 180nm technology node & 1.8V standard CMOS process. Comparison between these techniques has shown a significant power saving to the extent of 60% in case of Transmission gate logic design carry select adder , as compared to CMOS logic in 10- 100MHz transition frequency range.

Keywords - Adder, carry select Adder , Mux , T_SPICE , XOR gate

[1]. Chandrakasan, A.,Brodersen,"Low Power Digital Design",Kluwer Academic Publishers, R., 1995.
[2]. Low power cmos VLSI circuit design Kaushik Roy,sharatc.prasad copy right @2000 by john Wiley Sons Inc
[3]. AtulKumarMaury & Gagnesh Kumar, Energy Efficient Adiabatic Logic for Low Power VLSI Applications, 2011 International Conference on Communication Systems and Network Technologies.
[4]. Shipraupadhay,R.AMishra,RKNagari,andSPSingh,DiodefreeAdiabaticlogiccircuits,hindawanipublishedcorporationsISRNElectronicsVolume2013,ArticleID 673601.
[5]. O. J. Bedrij, "Carry-Select Adder", IRE Transactions one Electronic Computers, pp. 340–346, June 1962.

Paper Type : Research Paper
Title : Fault Tolerance in Network-on-Chip by Using Single Error Correction and Double Error Detection
Country : India
Authors : Geeta A Sannakki || Maltesh Bajantri

ABSTRACT: The emerging technique for communication with in a large VLSI system is a network on chip. The fast scaling of technique there has been susceptible faults in the component of the network on chip, thus there is a requirement for technique to maintain circuit reliability. A fault-tolerant NOC (Network-on-chip) should be having the capacity to detect a fault and recover the system to correctly operate and work according to the mapped application. The work performed here emphasizes on the learning and assessing of methods for growing flexibility of system interfaces with NOC based multi-processor system on chip (MPSOC) design. In between communication infrastructure and the IP cores, NIs (Network interface) acts as junction. The flawed action of one of the interface could affect or harm the overall system.

[1]. Chen, S.J., Lan, Y.C., Tsai, W.C, & Hu, Y. "Fault Tolerance in BiNoC". Springer. 2012. 157-171.
[2]. Collet, J.H., Louri, A., Tulsidas, V. & Poluri, P. "ROBUST: A new Self-healing Fault-Tolerant NoC Router". University of Arizona. 5-17.
[3]. Grecu, C., Anghel, L., Pande, P., Ivanov, A. & Saleh, R. "Essential Fault-Tolerance Metrics for NoC Infrastructures". International Online Testing Symposium. 2007. 1-6.
[4]. Koupaei, F.K., Khademsadeh, A. & Janidarmian, M. "Fault-Tolerant Application-Specific Network-on-Chip". Proceedings of the World Congress on Engineering and Computer Science. 2011. 1-5.
[5]. Lehtonen, P. Liljeberg, T, & Plosila,J. "Online reconfigurable self-timed links for Fault-tolerant NoC." VLSI Design. 2007. 1-13.

Paper Type : Research Paper
Title : Fusion based Fingerprint Recognition based on CLBP descriptor and DWT
Country : India
Authors : Shruthi A B || M G Srinivasa || Sheshagiri Jois

ABSTRACT: Biometric recognition presently becoming an important tool for human identification. Fusion based biometric identification is an emerging trend which leads to improved accuracy. In this paper, we propose Fusion based algorithm involving CLBP and DWT which are applied to the fingerprint images separately in order to extract the features. The extracted features are fused by concatenation in order to obtain unique features. These features are compared with the stored database for matching.

Keywords - Fusion, DWT, CLBP, Fingerprint, Biometric

[2] Nishant Singh, Kamlesh Tiwari, Aditya Nigam and Phalguni Gupta "Fusion of 4-SlapFingerprint Images with their Qualities for Human Recognition" 2012 World Congress on Information and Communication Technologies 2012 IEEE [3] Abdallah Meraoumia, Salim Chitroub and Ahmed Bouridane, "Fusion of Finger-Knuckle-Print and Palmprint for an Efficient Multi-biometric System of Person Recognition", IEEE Communications Society subject matter experts for publication in the IEEE ICC 2011 proceedings. [4] Ashraf A. Darwish, Walaa M.Zaki "Human Authentication using Face and Fingerprint Biometric", 2010 Second International Conference on Computational Intelligence, Communication Systems and Networks
[5] Zin Mar Win and Myint Myint Sein, "Texture Feature based Fingerprint Recognition for Low Quality Images", 2011 International Symposium on Micro-NanoMechatronics and Human Science IEEE [6] Yi (Alice) Wang and Jiankun, "Global Ridge Orientation Modeling for Partial Fingerprint Identification" IEEE Transactions on pattern Analysis and Machine Intelligence, vol. 33, no. 1, January 2011

Paper Type : Research Paper
Title : Image De-noising using Median Filter and DWT Adaptive Wavelet Threshold
Country : India
Authors : Ms.Dhanushree.V || Mr.M.G.srinivasa

ABSTRACT: Image de-noisingplays an important role in satellite communication and signal processing applications. In thispaper, we propose an medianfilter and adaptive wavelet thresholding shrinkage technique for image de-noising. The noisy image ispassedthroughpre-processingmedianfilter to remove the noise and twoleveldiscretewavelettransformisappliedwhichispassedthrough post-processingmedianfilter to remove noise. Finally, Bayes thresholding shrinkageisapplied to all sub-bands to obtain de-noised image. The Inverse discretewavelettransformisapplied to reconstruct the image. The Image qualityismeasured in terms of the PSNR and isobservedthat the proposedmethodobtainsbetter PSNR compared to existingmethod.

Keywords: Bayes shrinkage, DWT, median filter, PSNR, Denoise.

[1]. S.Deivalakshmi, S.Sarath and P.Palanisamy "Detection and Removal of Salt and Pepper noise in images by Improved Median Filter", 2011 IEEE
[2]. Liwen Dong "Adaptive Image Denoising Using Wavelet Thresholding" Third International Conference on Information Science and Technology March 23-25, 2013.
[3]. YungangZhang,Bailing Zhang and Wenjin Lu "Image Denoising and Enhancement Based on Adaptive Wavelet Thresholding and Mathematical Morphology" 2010 3rd International Congress on Image and Signal Processing.
[4]. MantoshBiswas and Hari Om" An Adaptive Wavelet Thresholding Image Denoising Method" 2013 IEEE
[5]. YaserNorouzzadeh and MasoudRashidi" Image Denoising in Wavelet Domain using a New Thresholding function" International Conference on Information Science and Technology March 26-28, 2011 Nanjing

Paper Type : Research Paper
Title : Design and Simulation of Double Precision Floating Point Division Using VHDL
Country : India
Authors : Bharti W.Sakande || Dinesh Rotake

ABSTRACT: This paper proposed the methodology for double precision floating point division using radix-8.This is the improved method of producing high speed. The architecture is based on look-up table and comparator. Double precision floating point division offer qualities like high speed on the expense of larger area and circuit complexity. Also floating point value can be represented by using IEEE-754 standard for division. This design will be simulated in Xilinx and it can be highly portable if it is design on a field programmable gate array (FPGA).

Keywords: Floating point unit, FPGA, IEEE-754, Radix-8, VHDL, Xilinx.

[1]. K.Scott Hemmert and Keith D.Underwood "Floating-Point Divider Design for FPGAs" IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol.15, No.1, January 2007.
[2]. ANSI/IEEE Standard 754-1985, IEEE Standard for Binary Floating-Point Arithmatic 1985.
[3]. Jitendra Soni, Ravi Mohan. ECE, SRIT, Jabalpur, India" Floating Point Single Precision Division in VHDL Environment" International Journal of Emerging Trends in Electronics and Computer Science (IJETECS) Volume 2,Issue 10,Oct.2013.
[4]. Riya Saini, Galani Tina G. and R.D. Daruwala" Efficient Implementation of Pipelined Double Precision Floating Point Unit on FPGA" International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 1, July-2013.
[5]. Nicolas Brisebarre, Jean-Michel Muller, Member, IEEE, and Saurabh Kumar Raina "Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in Advance" IEEE Transactions on Computers, Vol. 53, No. 8, August 2004.

Paper Type : Research Paper
Title : A new design 6T Full Adder Circuit using Novel 2T XNOR Gates
Country : India
Authors : Krishna Chandra || Rajeev Kumar || Shashank Uniyal || Vishal Ramola

ABSTRACT:Exclusive-NOR (XNOR) gates are important in digital circuits. This paper proposes the novel design of 2T XNOR gate using pass transistor logic. The proposed circuit utilizes the least number of transistors and no complementary input signals is used. The design has been compared with earlier designed XNOR gates and a significant improvement in silicon area and power-delay product has been obtained against 3T XNOR gate. Instead of cascading two two-input XNOR gates, we design a new structure of three-input function on the transistor level in this paper. A 6 transistor full adder has been designed using the proposed two-transistor XNOR gate. The performance has been investigated using 0.18μm Technology and evaluated by the comparison of the simulation result obtain from TSPICE.
Keywords: XNOR gate, Full adder, Delay, Power Delay Product.

[1] N. Weste and K. Eshraghian, Principles of CMOS VLSZ Design, Reading, MA: Addison-Wesley, 1985

[2] W. Jyh Ming, F. Sung-Chuan, and F. Wu-Shiung, "New efficient designs for XOR and XNOR functions on the transistor level," Solid- State Circuits, IEEE Journal of, vol. 29, pp. 780-786, 1994.

[3] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, ―New 4- transistor XOR and XNOR designs,‖ Tech. Rep., Florida Atlantic Univ., Boca Raton, 1999.

[4] Sreehari Veeramachaneni and Hyderabad, ―New improved 1-bit adder cells‖, CCECE/CCGEI, Niagara Falls. Canada, May 5-7 2008, pp. 735-738.

[5] J. Wang, S. Fang, and W. Feng, ―New efficient designs for XOR and XNOR functions on the transistor level,‖IEEE J. Solid-State Circuits, vol. 29, pp. 780–786, July 1994.

Paper Type : Research Paper
Title : Effects of Sputtering Process Parameters for PVD Based MEMS Design
Country : India
Authors : Dibyendu Roy || Niladri Halder || Tanumoy Chowdhury || Arnab Chattaraj || Pulakesh Roy

ABSTRACT: MEMS or micro-electro-mechanical system is a widely used technology for manufacturing devices in micro range. This technology combines electrical and mechanical properties on a single chip. The most crucial step in MEMS fabrication process includes the deposition of device material on substrate by suitable deposition techniques [1]. So, present study intends to investigate the deposition of Ni, Ti and Cu based ternary thin film materials on Si (100) substrate for the fabrication of MEMS devices using classical molecular dynamics simulation, and also to study the variation of film structure and properties by varying its different process parameters like substrate temperature and substrate bias voltage etc [2-3].

[1]. B Geetha Priyadarshini, Shampa Aich, Madhusudan Chakraborty(2011),Structural and morphological investigations on DC-magnetron sputtered nickel films deposited on Si (100), Journal of Materials Science, 46, 2860
[2]. Hoo-Jeong Lee and Ainissa G. Ramireza(2004), Crystallization and phase transformations in amorphous NiTi thin films for microelectromechanical systems, APPLIED PHYSICS LETTERS VOLUME 85, NUMBER 7
[3]. J.Z. Chen, S.K. Wu(1999),Crystallization behavior of r.f.-sputtered TiNi thin fillms, Thin Solid Films 339, 194±199
[4]. R.m.s. martins,N. schell,A. m. ucklich, H. reuther, M. beckers, R.j.c. silva,I. pereira, F.m. braz fernandes(2008), Study of graded Ni-Ti shape memory alloy filmgrowth on Si(100) substrate, Appl. Phys. A 91, 291–299,Material Sc. & Processing
[5]. B.Geetha Priyadarshini, Shampa Aich, Madhusudan Chakraborty(2011), Studies on Ni-Ti Thin Films grown by Bias Assisted Magnetron Sputtering, TMS 2011 140th Annual Meeting and Exhibition, Supplemental Proceedings: Materials Processing and Energy Materials, Volume 1, John Wiley & Sons, Inc., Hoboken, NJ, USA 77–86

Researcher can also search IOSR published article contents through

IOSR Xplore