Abstract: The reversible logic has received great attention in last few years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design. Multipliers are widely used in DSP for calculation of FFT, convolution, to perform MAC operation, and in microprocessors to perform ALU related operations. This paper proposes a 16X16 reversible multiplier using Toffoli gate Full adder which can multiply two 16-bit numbers. It is based on the two concepts............
Keywords: Reversible Logic, Reversible Gate, Power Dissipation, Garbage
[1]. Nagamani A N, Ashwin S, Vinod Kumar Agrawal, " Design of Optimized Reversible Binary and BCD Adders", International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Journal of Research and Development, pp.124-129, 2015.
[2]. R. Landuer, "Irreversibility and heat generation in the computing process", IBM, J. Res. Develop., Vol. 5 , pp. 261-269, 1961.
[3]. C. H. Bennet, "Logical reversibility of computation", IBM, J. Res. Develop., Vol. 17(6), pp. 525- 532, 1973.
[4]. Barenco A, Bennett C.H, Cleve R, DiVincenzo D.P, Margolus N, Schor P, Sleator T, Smolin J, and Weinfurter H, "Elementary Gates for quantum computation", Physical Review A, pp. 3457 – 3467, 1995.
[5]. Kai-Wen Cheng and Chien-Cheng Tseng, "Quantum full adder and subtractor", Electronics Letters, Vol. 38(22), pp. 1343- 1348, 2002