IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

July - Aug 2014 Vol 4 - Issue 4

Version 1 Version 2 Version 3

Paper Type : Research Paper
Title : Advancements in Gesture Recognition Technology
Country : India
Authors : Poluka Srilatha, Tiruveedhula Saranya
: 10.9790/4200-04410107     logo
ABSTRACT: Gesture recognition is an upcoming technology which can change entire technology and our work in daily life. Gesture means signs made by human beings which originate from face, hands or any part of the body. These gestures can be captured using scanning or video methods and by processing these gestures in to human signals. GUI related interfaces are used in which text is taken as input from mouse and keyboard. In this new system gestures are used as inputs which do not require any mechanical elements to communicate between man and machine. If we move our hand on computer screen and based on our movement, curser will accordingly move which will make work easier. But now with increase in technological knowledge, the concept slowly enhanced into voice, speech recognition and position recognition models. These have enriched the domain and have roped in some very sophisticated means of human computer interaction. Finger tracking is one such advanced gesture innovation. It is the use of hands and their various positions to kick-start a computer application. It aims at minimizing the use of keyboard and mouse. Non-touch based interaction or giving the input to computers with eyes is one major breakthrough in the domain. It can certainly be adjudged as the ray of hope for disabled people or people busy with multitasking.
Keywords: Algorithm, AllSee, GUI, HMI, sign language



Paper Type : Research Paper
Title : Establishing the presence of Cardiac Sub-Harmonics and its Importance in detecting Cardiac Abnormalities
Country : India
Authors : Anandarup Mukherjee, Disha Singhania, Nidhi Pathak, Parakh Khandelwal
: 10.9790/4200-04410815     logo

ABSTRACT: This paper presents a novel method for detecting cardiac abnormalities in a way which is both non- invasive and low cost. This method utilizes the presence of harmonics generated within the human heart as indicators of possible cardiac abnormalities such as cardiac blocks or cardiac valve dysfunctions. Our work is divided into two sections; firstly, the establishment of the fundamental frequency of the human heart along with its associated sub-harmonics and secondly, the presence of various harmonics in normal and abnormal cardiac signals which may serve as possible indicators to determine cardiac dysfunctions. Our method was applied on Phonocardiograph (PCG) signals of patients with various cardiac conditions.

Keywords: Curve Fitting, Fourier Series, Frequency Spectrum, Harmonics, Phonocardiogram

[1] Howard B. Sprague, M.D., Patrick A. Ongley, M.D., "The Clinical Value of Phonocardiography", Circulation. 1954;9:127-134
[2] Sandra LachArlinghaus, PHB Practical Handbook of Curve Fitting. CRC Press, 1994.
[3] William M. Kolb. Curve Fitting for Programmable Calculators. Syntec, Incorporated, 1984
[4] C. Chatfield (1989). The Analysis of Time Series—An Introduction (fourth ed.). Chapman and Hall, London. pp. 94–95. ISBN 0-412-
[5] Hannan, E.J., "Stationary Time Series", in: John Eatwell, Murray Milgate, and Peter Newman, editors, The New Palgrave: A
Dictionary of Economics. Time Series and Statistics, Macmillan, London, 1990, p. 271.

Paper Type : Research Paper
Title : Domino Logic Topologies of OR Gate with Variable Threshold Voltage Keeper
Country : India
Authors : Vijay Singh Rathor ,Saurabh Khandelwal, Shyam Akashe
: 10.9790/4200-04411622     logo

ABSTRACT: In this paper, we tend to take four domino circuit topologies to boost the strength and lower the consumption of power. A high speed and noise immune domino logic circuit is given that uses the property of the footer semiconductor to raise the sensitivity of the dynamic node to noise and eventually in improved performance. Dynamic logic circuits are used for prime performance and high speed applications. We tend to analyze and compare completely different domino logic style topologies for lowering the sub-threshold outpouring current in standby mode NMOS block , increasing the speed and increasing the noise immunity. We tend to compare power, delay, and Power Delay Product (PDP) of various topologies. Simulation is finished employing a 45nm cadence tool for eight input OR circuit. Our projected circuits scale back power consumption by 100 percent to 35 the troubles, improvement of unity noise gain of 39% to 85% and have a higher figure of advantage as compared to conditional keeper domino. The simulation results unconcealed that prime Speed Conditional keeper Domino (CKD) circuit offers the most effective ends up in terms of reduction in delay and power consumption as compared to different circuits.

Key words: CMOS, domino logic, keeper ratio, Standby power, Noise immunity, Lower power design

[1]. Roy, K., S. Mukhopadhyay and H. Mahmoodi, 2002. Leakage curreent in deep-submicron CMOS circuits, Journal of Circuits, Syst. Comput, 11(6): 575-600.
[2]. De, V. and S. Borkar, 1999. Technology and design challenges for low power and high performance, in Proc. Int. Symp. Low Power Electronics and Design, pp: 163-168.
[3]. Anders, M., R. Krishnamurthy, R. Spotten and K. Soumyanath, 2001. Robustness of sub-70nm dynamic circuits:Analytical techniques and scaling trends, in Proc.Symp. VLSI Circuit, pp: 23-24.
[4]. Wairya, S., R.K. Nagaria and S. Tiwari, 2012. Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design, full adder circuits for low voltage VLSI design.
[5]. Kao, J.T. and A.P. Chandrakasan, 2000. Dual- threshold voltage techniques for low power digital circuits, IEEE Journal of Soloid-State Circuits, 35(7): 1009-1018.

Paper Type : Research Paper
Title : Design and Characterization of Third Generation Current Conveyor
Country : India
Authors : Payal shah, Amisha Naik
: 10.9790/4200-04412328     logo

ABSTRACT: This paper presents a low power low voltage positive third generation current conveyor using four simple first generation current conveyors. It is designed and simulated in a standard 0.18um TSMC 1P, 6M CMOS process. This current conveyor design with the help of design architect and IC station (mentor graphics). Its DC, AC and transient analysis is carried out with ELDO tool. Its pre layout and post layout results are also given.

Keywords: Current mode circuit, third generation current conveyor

[1]. FABRE, A.: "Third-generation current conveyor: A new helpful active element‟, Electron. Lett.. 1995, 31, (9, pp. 338-339
[2]. BRUUN, E.: "Class AB CMOS first-generation current conveyor‟, Electron. Lett.. 1995, 31, (6), pp. 422423
[3]. A. Piovaccari, "CMOS integrated third-generation conveyor," Electronics Letters, Vol. 31, No. 15, pp. 1228-1229, 1995.
[4]. Giuseppe Ferri and Nicola C. Guerrini."Low Voltage Low Power CMOS Current Conveyors"by Pg no.126-128
[5]. Kimmo Koli,,''CMOS Current Amplifiers:Speed versus Nonlinearity",Ph.D,Dissertation,Helsinki University of Technology,Finalnd,Oct-2000.

Paper Type : Research Paper
Title : A Survey of Recent Embedding Techniques and Security Measures in Steganography
Country : India
Authors : Gudapati Sri Kali
: 10.9790/4200-04412931     logo

ABSTRACT: Steganography is an act of hiding a message, image or file in another message, image or file such that only the intendant sender and receiver know the existence of the secret message. Steganography takes the advantage of the redundancy of data in the cover media to insert the secret data. The steganography requires sufficient embedding capacity as well as security. This paper revises different embedding techniques most popularly used and the security measures to enhance the goal of steganography.

Index Terms: Steganography, Cryptography, Payload

[1]. J. Fridrich, Steganography in Digital Media: Principles, Algorithms, and Applications. Cambridge, U.K.: Cambridge Univ. Press, 2009.
[2]. N. Provos and P. Honeyman, "Hide and seek: An introduction to steganography," IEEE Security Privacy, vol. 3, no. 3, pp. 32–44, May/Jun. 2003.
[3]. Bin Li, Junhui He, Jiwu Huang, Yun Qing Shi, "A Survey on Image Steganography and Steganalysis", Journal of Information Hiding and Multimedia Signal Processing, Vol.2, Issue 2, pp. 142-172, April 2011.
[4]. Chi-Kwong Chan, L.M. Cheng, "Improved hiding data in images by optimal moderately signifcant-bit replacement", IEE Electron Lett. 37 (16) (2001) 1017–1018.
[5]. Chi-Kwong Chan, L.M. Cheng, "Hiding data in images by simple LSB substitution", Pattern Recognition, Vol.37, pp. 469-474, 2010.
[6]. X. Zhang and S. Wang, "Efficient steganographic embedding by exploiting modification direction," IEEE Commun. Lett., vol. 10, no. 11,pp. 781–783, Nov. 2006.

Paper Type : Research Paper
Title : Zigbee Based Underground Mines Parameter Monitoring System for Rescue and Protection
Country : India
Authors : Pranoti Anandrao Salankar, Sheeja S. Suresh
: 10.9790/4200-04413236     logo

ABSTRACT: This paper based on continuous monitoring underground coal mines parameter such as carbon monoxide, temperature, water level and use wireless Zigbee technology for communication. A microcontroller based system is used for collecting and storing data using respective sensors and making decision accordingly, based on which the mine worker is informed through different alarm tone as well as LED display system. The communication system is reliable based on zigbee, IEEE 802.15.4 standard.

[1]. "The Research on ZigBee-Based Mine Safety Monitoring System"by Ge Bin, LI Huizong. 978-1-4244-8039-5/11[2011]
[2]. IEEE paper on "A Coal Mine Environmental Monitor System with Localization Function Based on ZigBee-Compliant Platform" by Dongxuan Yang, Yan Chen, Kedong Wang. 978-1-4244-6252-0/11/ ©2011 IEEE
[3]. [3]"Design of the mine gas sensor based on zigbee" by Su baishun, Pang Zhengduo, MengGuoying [August 10].ISBN 978-952-5726-10-7
[4]. IEEE paper on "Zigbee based intelligent helmet for coal miners" by CHENG Qiang, sun ji_ping, zhangzhe, zhang February [2009] CSIE2009.653
[5]. "Rescue and protection system for underground mine workers based on zigbee" by Tanmoymaity, parthasarathi das, mithumukherjee, vol.2 no.2 [June_December,2012] int.jr.of advanced computer eng.& architecture
[6]. "Wireless Networking ThroughZigbee Technology" by P.Rohitha, P. Ranjeet Kumar Prof.N.Adinarayana, Prof.T.VenkatNarayanaRao ISSN: 2277 128X vol.2 [7 July 2012].

Paper Type : Research Paper
Title : Design of ARM7 Based Traffic Control System
Country : India
Authors : Ashwini Y. Dakhole,Dr.U.M.Gokhale, Prof. MrunaliniP. Moon
: 10.9790/4200-04413440     logo

ABSTRACT: The increase in urbanization and traffic congestion creates an urgent need to operate our transportation systems with maximum efficiency. One of the most cost-effective measures for dealing with this problem is to adopt favorable traffic signal control strategies.The main objective of this research is to develop an effective procedure to control the traffic which tries to reduce possibility of traffic jams, caused by traffic light delay and to detect the emergency cars such as fire engines and ambulances and have priority over other traffic. This system gives highest priority to emergency vehicles to pass them. The system is based on ARM7 and AT mega 16. Keywords: ARM7, AT mega 16, RF module, IR sensors.

[1]. Xu Li, Wei Shu, Minglu Li, Hong-Yu Huang, Pei-En Luo, and Min-You Wu, "Performance Evaluation of Vehicle-Based Mobile Sensor Networks for Traffic Monitoring" IEEE 2009
[2]. SamySadeky, Ayoub Al-Hamadiy, Bernd Michaelisy, UsamaSayedz,"Real-time Automatic Traffic Accident Recognition Using HFG", 2010 International Conference on Pattern Recognition
[3]. Malik Tubaishat, Qi Qi, Yi Shang, Hongchi Shi "Wireless Sensor-Based Traffic Light Control", IEEE 2008
[4]. Zhang Yuye,YanWeisheng"Research of Traffic Signal Light Intelligent Control System Based On Microcontroller" IEEE 2009
[5]. Manoj KantaMainali& Shingo Mabu (2010) "Evolutionary Approach for the Traffic Volume Estimation of Road Sections", pp100- 105, IEEE .

Paper Type : Research Paper
Title : Design Modulo-4 and Galois Field Adder, Subtractor and Multiplier Using Quaternary Logic
Country : India
Authors : Miss. Rajashri R. Korde, Asst.Prof. Dinesh Rotake
: 10.9790/4200-04414152     logo

ABSTRACT: Arithmetic circuits play a very necessary role in every general and application specific procedure circuits. Multiple Valued Logic (MVL)provides the key smart factor concerning future density per circuit area compared to ancient two valued binary logic. Quaternary (Four-valued) logic jointly offers the nice factor concerning easy interfacing to binary logic as a results of base four (=22) permits for the use of easy encoding/decoding circuits. The purposeful completeness is proved with a set of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) unit of measurement designed, simulated, and accustomed build several quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells unit of measurement valid practice SPICE models and additionally the arithmetic architectures unit of measurement valid practice System Verilog models for purposeful correctness. Quaternary (radix-4) twin amount secret writing principles unit of measurement applied to optimize power and performance of adder circuits practice common place cmos gate technologies.

Index Terms: Multiple-valued logic , Quaternary logic, Modulo-n addition , subtraction and multiplication, Galois. Addition and multiplication

[1]. Vasundara Patel K.S, K.S. Gurumurthy, "Design of high performance Quaternary adders",IEEE, International Conference on Advances in Computing, Control and Telecommunication Technologies, pp.22-26. IEEE 2011.
[2]. Vasundara Patel K.S, K.S. Gurumurthy, "Multivalue Logic Addition and Multiplication In Galois Field", IEEE, International Conference on Advances in Computing, Control and Telecommunication Technologies, pp.752-755, IEEE 2009.
[3]. Satyendra R. Datla, "Quaternary Addition Circuits Based on SUSLOC Voltage Mode Cells and Modeling with System Verilog", 39th International Symposium on Multiple Valued Logic, IEEE, 2009.
[4]. Mahsa Dornajafiet al. " Performance of a quaternary logic design ", IEEE Region Conference, pp.1-6, IEEE April 2008.
[5]. Dakhole P. K,Wakde D. G. "Multi-Digit Quaternary Adder on Programmable Device: Design & Verification", International confe-rence on Electronic Design, P enang, Malaysi, December pp. 1-3, IEEE 2008.

Paper Type : Research Paper
Title : Performance Analysis of Low Power Bypassing-Based Multiplier
Country : India
Authors : Anupa.S.Kavale, Asst.Prof. Dinesh Rotake, Asst.Prof. M. M. Mahajan
: 10.9790/4200-04415358     logo

ABSTRACT: In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power is to be achieved in changed partial products of column bypassing multiplier as compared to column bypassing multiplier by exchange NOR gates with AND gates in the conventional multiplier I.e. in the design of conventional multiplier rather than AND gate, NOR gate is employed victimization DeMorgan's theorem. Compare with 32×32 bits typical (parallel array) multiplier and column bypassing multiplier, this planned system consume less power.
Keywords: changed column bypassing multiplier, conventional multiplier.

[1]. Jin-Tai Yan, Zhi-Wei Chen," Low-Cost Low-Power Bypassing-Based Multiplier Design", 978-1-4244-5309-2/10/$26.00 ©2010 IEEE
[2]. J. T. Yan and Z. W. Chen, "Low-power multiplier design with row and column bypassing," IEEE International SOC Conference, pp.227-230, 2009.
[3]. M. C. Wen, S. J. Wang and Y. M. Lin, "Low power parallel multiplier with column bypassing," IEEE International Symposium on Circuits and Systems, pp.1638-1641, 2005.
[4]. J. Ohban, V. G. Moshnyaga, and K. Inoue, "Multiplier energy reduction through bypassing of partial products," IEEE Asia-Pacific Conference on Circuits and Systems, pp.13–17, 2002.
[5]. J. Ohban, V. G. Moshnyaga, and K. Inoue, "Multiplier energy reduction through bypassing of partial products," IEEE Asia-Pacific Conference on Circuits and Systems, pp.13–17, 2002.

Paper Type : Research Paper
Title : "CMOS Form of Wallace Range Exploitation Domino Logic Full Adder"
Country : India
Authors : Deepali S. Kolhe, Prof. U.M. Gokhale, Prof. Shweta thakur
: 10.9790/4200-04415963     logo

ABSTRACT: The main objective of this project is to provide new low power solution for very large scale integration (VLSI) designer. Especially, this work focuses on the reduction of power dissipation, which is showing an ever increasing growth with the scaling down of the technology. Various technologies at the different level of the design process have been implemented to reduce power dissipation at the circuit, architectural and system level. It permits for commencement of analysis during a procedure block before its analysis section begins, and quickly performs a final analysis as shortly because the inputs are valid. This dynamic logic family is best suited to arithmetic circuits as a result of the important path is created of a protracted chain of cascaded inverting gates. Because the major advantage of this logic that is higher speed is discovered upon cascading, it's most fitted for arithmetic circuits using submicron technology.

Keyword: Domino Logic, Wallace Multiplier, Power Dissipation, Full Adder, CMOS Logic

[1] Gaetano Palumbo, Melita Pennisi, and Massimo Alioto, "A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 59, NO. 10, pp 2292-2300,OCTOBER 2012.

[2] Rahul Singh, Gi-Moon Hong, and Suhwan Kim," Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 60, NO. 4, APRIL 2013.

[3] Skyler Weaver, Benjamin Hershberg, Nima Maghari, and Un-Ku Moon, "Domino- Logic-Based ADC for Digital Synthesis", ", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 58, NO. 11, pp 744-747, NOVEMBER 2011.

[4] Ali Peiravi and Mohammad Asyaei," Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates", IEEE TRANSACTION ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,VOL. 21, NO. 5, pp934-943, MAY 2013.

[5] Neil H.E Weste, David Harris, Ayan Banerjee, "CMOS VLSI DESIGN" Third edition, Pearson Education 2006

Paper Type : Research Paper
Title : A Survey on Static Power Reduction Techniques in Asynchronous Circuits
Country : India
Authors : V. Madhurima, Dr. Kesari Padma priya
: 10.9790/4200-04416469     logo

ABSTRACT: With the technology down scaling the area of each device in a chip reduces. Lesser area increases the power consumption. In current technologies leakage current is the major part in power consumption. Power gating is a technique which has been used to reduce leakage power by shutting off the power when no activity done by the logic. These helps to reduce the power consumption, delay and switching times of the logic. This survey paper mentions the different techniques to reduce leakage power in asynchronous logic.

Keywords: Asynchronous logic, power gating, sleep mode etc.

[1]. G Tellez, A Farrahi, and M Sarrafzadeh. Activity-driven clock design for low power circuits. ICCAD, pages 62 – 65, Nov 1995.
[2]. Fatih Hamzaoglu and Mircea Stan. Circuit-level techniques to control gate leakage for sub-100nm cmos. ACM ISLPED, Aug 2002.
[3]. K Roy, S Mukhopadhyay, and H Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits. Proc. IEEE, 91(2):305 – 327, Feb 2003.
[4]. A Keshavarzi, K Roy, and C Hawkins. Intrinsic leakage in low power deep submicron cmos ics. IEEE ITC,pages 146 – 155, Nov 1997.
[5]. K Shi and D Howard. Sleep transistor design and implementation – simple concepts yet challenges to be optimum. IEEE VLSI-DAT, pages 1 – 4, Apr 2006.

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