IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Sep-Oct. 2017 Vol 7 - Issue 5

Version 1

Paper Type : Research Paper
Title : Fetal Heartbeat Signal Extraction using an Adaptive Noise Canceller implemented with an improved Simulated Annealing Algorithm
Country : Kenya
Authors : Mr. Kevin Mwongera || Dr. Kibet Langat || Dr. E. N. Ndung'u
: 10.9790/4200-0705010111     logo

ABSTRACT: Measured fetal heartbeat signals are usually contaminated by the corresponding mother's heartbeat signal and other random noise. Adaptive Noise Cancellation (ANC) is usually employed in extraction of fetal heartbeat signals from signal measurements taken at the mother's abdomen. A variety of algorithms can be utilized in ANC to yield minimal-noise fetal heartbeat signals. An ideal algorithm ought to generate an accurate result in as little time as possible. In this paper, an improved Simulated Annealing (SA) algorithm is utilized in ANC to yield a minimal-noise fetal electrocardiogram signal in MATLAB. A performance analysis between use of the improved SA algorithm and the standard SA algorithm (alongside Genetic, Least Mean Squares (LMS) and Normalized Least Mean Squares (NLMS) algorithms) is done. The improved SA algorithm is found to outperform the other algorithms...........

Keywords: Adaptive Noise Cancellation, Genetic Algorithm, Least Mean Squares algorithm, Normalized Least Mean Squares algorithm, Simulated Annealing algorithm..

[1] A. Singh, Adaptive noise cancellation, 1st ed.: Netaji Subhas Institute of Technology, 2001.
[2] S. Haykin, Adaptive Filter Theory, 4th ed. New Jersey: Prentice Hal, 2002.
[3] M. G. Bellanger, Adaptive Digital Filters, 2nd ed.: Marcel Dekker, 2001.
[4] S. K. Patrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Journal of Science, vol. 220, no. 4598, pp. 671-
680, 1983.
[5] A. Emile, K. Jan, and M. Wil, Search Methodologies: Introductory Tutorials in Optimization and Decision Support Techniques, 1st
ed.: Springer, 2014.

Paper Type : Research Paper
Title : FPGA Based Moving Object Tracking For Indoor Robot Navigation
Country : India
Authors : T. D. Magdum || P. C. Bhaskar
: 10.9790/4200-0705011222     logo

ABSTRACT: Indoor environments such as houses, offices, hospitals, mobile robots have to be equipped with a capability to navigate in indoor environments to execute a given task while avoiding obstacles. A number of sensors are used widely in order to navigate while detecting obstacles in indoor environments. However, most of these sensors are too expensive to apply for low-cost service robots. Thus we can use low cost surveillance camera for indoor robot navigation using the visual navigation. This paper gives the state of the art the FPGA and indoor robot navigation concept with the focus on FPGA based moving object tracking. The paper starts with an overview of FPGA base image processing in order to get an idea about FPGA architecture, and followed by an explanation on Moving object tracking algorithm and virtual path claculation. Finally, we concluded FPGA is an ideal choice for implementation of visual navigation for real time moving object tracking algorithms.

Keywords: FPGA implementation, Indoor navigation, Moving object tracking algorithm, Virtual path claculation

[1]. Pujari Shashank, Bhandari Sheetal, Chandak Sudarsan (2008), "FPGA Controlled Vision System for Survillance Robot (UAV)", CSI Communication, Robotics, Nov. 2008, Vol32
[2]. Nguyen Xuan Dao, Bum-Jae You, Sang-Rok Oh, "Visual navigation for indoor mobile robots using a single camera".
[3]. Jung Uk cho, Seung hun jin, Xuan Dai Pham, Dong kyun Kim, and jae wook Jeon (2007), "FPGA Based Real Time Visual Tracking System using Adaptive color Histograms", IEEE, 2007.
[4]. Rao Sandeep, Natarajan Aranind, Moorthi S.and Selvan M. P.(2012), "Real Time Object Tracking in a video Stream using Field Programmable Gate Array", IEEE, 2012.
[5]. Pandey Monoj , Bprgohain Dorothi, Baruah Gargi (2013), "Real Time Object Tracking : Simulation and Implementation on FPGA Based Soft Processor", ICSSITE, 2013.

Paper Type : Research Paper
Title : An Efficient and Noninvasive Method to Extract Fetal Electrocardiogram from Abdominal Electrocardiogram
Country : India
Authors : Esha Ahuja || Faisal Shaikh
: 10.9790/4200-0705012326     logo

ABSTRACT: Monitoring health of fetus has become very important these days as many diseases are observed just after the delivery of baby. This is even causing death of baby if the disease remains undetected and hence uncured. Hence to know the well-being of fetus, the proposed method is to acquire the fetus's ECG and observing it doctors can get an idea of fetus's health. In the present paper, we describe a non-invasive method to extract Fetal ECG from mother's abdominal ECG. This method is compared with results of other methods and found efficient comparatively.

Keywords: Blind Source Separation (BSS), Fetal Electrocardiogram (FECG), ICA (Independent Component Analysis), Mother's Abdominal Electrocardiogram (MECG), Noninvasive.

[1] Dina Shehada, and Ahsan H. Khandoker, "Non-Invasive Extraction of Fetal Electrocardiogram Using Fast Independent Component Analysis Technique," presented at the Middle East Conference on Biomedical Engineering, Doha, Qatar, February 17-20, 2014.
[2] R. K. Paithane, and F. I. Shaikh, "A Modified approach to FECG Extraction Using Sequential and Parallel Kalman Filter," IRJET, vol. 3, pp. 2440-2443, April 2016.
[3] R. M. Clemente, J. L. Camargo-Olivares, and S. Hornillo-Mellado "Fast Technique for Noninvasive Fetal ECG Extraction," IEEE Trans. Biomedical Engineering, vol. 58, pp. 227-230, Feb. 2011.
[4] A. K. Barros, and A. Cichocki, "Extraction of Specific Signals with temporal Structure," Neural Computation, MIT Press, 2001.
[5] R.Sameni and G. Clifford, "A Review of Fetal ECG Signal Processing Issues and Promising Directions," The Open Pacing, Electrophysiology and Therapy Journal, Vol. 3, pp 4-20, 2010.

Paper Type : Research Paper
Title : An Average power Estimation Technique for Integrated Circuits
Country : India
Authors : Dr. B. Mohan Kumar Naik
: 10.9790/4200-0705012729     logo

ABSTRACT: As world is moving along with electronics, designing VLSI circuits, accurately estimate the silicon area and the expected performance are become most important analysis before the circuit goes into fabrication. The requirements for low power, makes the designers to analyze and optimize the MOS structures and their designs with respect to power dissipation. The accurate estimate of power dissipation at different levels is the design abstraction. In this paper the estimation of average power in MOS circuits. The circuit reliability gives an average power of battery life while maximum or peak power is related to performance of the circuit and the proper design of power and ground lines.

[1]. V. D. Agrawal, "Low-Power Design by Hazard Filtering," in Proc. Tenth International Conf. on VLSI Design, Jan. 1997, pp. 193–197.
[2]. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, "Digital Circuit De- sign for Minimum Transient Energy and a Linear Programming Method," in Proc. Twelfth International Conference on VLSI Design, Jan. 1999, pp. 434–439.
[3]. V. Bartkute and L. Sakalauskas, "Three Parameter Estimation of the eibull Distribution by Order Statistics," in C. H. Skiadas, editor, Recent Advances in Stochastic Modeling and Data Analysis, pp. 91–100, World Scientific, 2007.
[4]. J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski, "System Simulation with MIDAS," AT&T Tech. J., vol. 70, no. 1, pp. 36–51, Jan. 1991.
[5]. L. Bisdounis, S. Nikolaidis, and O. Loufopavlou, "Propagation Delay and Short-Circuit Power Dissipation Modeling of the CMOS Inverter," IEEE Trans. Circuits and Systems I: Funda- mental Theory and Applications, vol. 45, no. 3, pp. 259–270, Mar. 1998

Paper Type : Research Paper
Title : Implementation of Low Power Voltage Level Shifter Using GALEOR Technique for Subthreshold Operation
Country : India
Authors : Jalla Chinnari || Hanumantha Rao Sistla
: 10.9790/4200-0705013035     logo

ABSTRACT: The Voltage Level Shifter is widely used in various integrated circuits these days such as in analogue computers, simulation systems and in many electronic applications as filtering, buffering and comparison of signal levels. Basically voltage level shifter converts low levels of input voltages in to high output voltage levels. In this paper various types of voltage level shifters are discussed mainly focus on the power efficient voltage level shifter, before this architecture explain the architecture of high speed voltage level shifter. To reduce the power consumption implement voltage level shifter with GALEOR technique. GALEOR (Gated LEakage TransistOR), reduces the leakage current flowing through the circuits. new static power reduction technique named GALEOR, which reduces the leakage current flowing through the circuit by creating a stack effect using high threshold voltage transistors in between the pull..........

Keywords: level shifter, subthreshold, analog blocks, latch state, auxiliary circuit

[1]. D. Zhang and A. Bhide: "A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13um cmos for medical implant Devices," IEEE j. solid-state circuits, vol. 47, no. 7, pp.1585-1593, July 2010.
[2]. K. Usami et al., "Automated low-power technique exploiting multiple supply voltages applied to a media processor," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 463–472, Mar. 1998.

[3]. Y. osaki, T. Hirose, N. Kuroki and M. Numa: "A low power level shifter with logic error correction for extremely low-voltage digital cmos LSIs," IEEE j. solid-state circuits, vol. 47, no. 7, pp.1776-1783, July 2012.
[4]. S. R. Hosseini, M. Saberi, and R. Lotfi: "A low-power subthreshold to above-threshold voltage level shifter"IEEE Trans. Circuits Syst. II, Exp. Brief, vol.61, no. 10, pp. 753-757, Oct 2014.
[5]. P. Corsonello, S. Perri, and F. Frustaci, "Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology," in Proc. IEEE Int. Conf. Comput. Design (ICCD), Oct. 2015, pp. 499–504.

Paper Type : Research Paper
Title : Color Image Implementation of Guided Filter Derived By Local Linear Model
Country : India
Authors : Aparna Lahane || Dr.V.B.Malode
: 10.9790/4200-0705013639     logo

ABSTRACT: Filtering is widely used in image processing for various applications now. The guided filter has been proposed and became one of the popular filtering methods. Derived from a local linear model, the guided filter generates the filtering output by considering the content of a guidance image, which can be the input image itself or another different image .Image Enhancement is one of the most important and difficult techniques in digital image Processing. Image Enhancement is used for improve the quality. Guided filter uses the color........

Keywords: Color image, Image Enhancement, Image Smoothing, MATLAB, VHDL

[1] Chieh-chi kao, Jui-hsinlai, "VLSI architecture design of guided filter for 30 frames/s FULL-HD video", IEEE transactions oncircuits and systems for video technology, vol. 24, no. 3,March 2014, pp.513- 524 .
[2] Kaiming He, Jian Sun, "Guided Image Filtering", IEEE Transactions On Pattern Analysis and Machine Intelligence, vol. 35, no. 6, ,June 2013, pp.1397-1409.
[3] Tomasi, C., Manduchi, R.: Bilateral filtering for gray and color images. ICCV (1998)C. Liu, W. Freeman, R. Szeliski, and S. B. Kang, "Noise estimation from a single image," in Proc. IEEE CVPR, vol. 1, 2006, pp. 901–908.
[4] F. Durand and J. Dorsey, "Fast bilateral filtering for the display of highdynamic- range images," ACM Trans. Graph., vol. 21, no. 3, Jul. 2002, pp. 257–266.
[5] Z. Farbman, R. Fattal, D. Lischinski, and R. Szeliski, "Edge-preserving decompositions for multiscale tone and detail manipulation," ACM Trans. Graph., vol. 27, no. 3,:10, Aug. 2008, pp. 67:1–67..

Paper Type : Research Paper
Title : Carbon Nanotubes FET based high performance Universal logic using Cascade Voltage Switch Logic
Country : India
Authors : Mitali Sharma || Rajesh Mehra
: 10.9790/4200-0705014047     logo

ABSTRACT: The paper proposes the design of efficient universal logic gates for nanotechnology. The basic component used in the design is Carbon Nanotubes instead of the conventional silicon based units. The extraordinary properties of the carbon nanotubes such as high thermal & electrical conductivity, flexibility, high tensile strength provides the added advantages for adopting the CNTs for the design of electronic circuits. Along with these properties, the CNTs give a great opportunity of scaling the circuit design to the nano regime. The logic gate designed using the CNFETs along with cascade voltage switch logic had proved to be an achievement that can be further taken to the high end complex circuits. The design of the logic gate proposed in this paper is designed using the 32nm Stanford CNFET technology and is compared with the conventional CMOS based CVSL circuits. The parameters........

Keywords: CNFET, CVSL, NAND Gate, NOR gate

[1] B.K. Kaushik, M.K. Majumder, ―Carbon Nanotube Based VLSI Interconnects‖, Springer Briefs in Applied Sciences and Technology, pp. 17-37, 2015.
[2] Rajendra Prasad Somineni, Y Padma Sai, S Naga Leela, ―Low leakage cntfet full adders‖, IEEE Proceedings of Global Conference on Communication Technologies, pp. 174-179, April 2015.
[3] Swati Sharma, Rajesh Mehra, ―Area & Power Efficient Design of XNOR-XOR Logic Using 65nm Technology‖, National Conference on Synergetic Trends in engineering and Technology, pp. 57-60, April 2014.
[4] Atheer Al-Shaggah et. All, ―Carbon Nanotube Field effect Transistor Models Performance and Evaluation‖, IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, pp. 8-13, December 2013.
[5] Ronak Zarhoun, Mohammad Hossein Moaiyeri, Samira Shirinabadi Farahani, and Keivan Navi, ―An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs‖, Electronics and Telecommunications Research Institute Journal, Volume 36, Number 1, pp. 89-98, February 2014..

Paper Type : Research Paper
Title : Multiple Constant Multiplication Architecture Using Graph Based Algorithm
Country : India
Authors : Sri Saikiran || Gurusiddayya Hiremath || Praveen Kumar M
: 10.9790/4200-0705014852     logo

ABSTRACT: Efficient algorithms and architectures exist for the design of low-complexity bit-parallel multiple constant multiplications (MCM). This operation dominates the complexity of many digital signals processing system. Alternative to this, digit-serial MCM design is available with less complexity. But it is not as much popular as the former one. Here the gate –level area and power of digit-serial MCM design is tried to optimize. So initially from the basic parallel designs, like shift –adds implementation, the common sub-expression elimination and graph-based method are used. From this the efficient one is selected, that is the GB technique and is applied to digit-serial design. Then........

Keywords: Cadence,Multipliers,MCM,Xilinx.

[1]. L. Aksoy, E. Costa, P. Flores, and J. Monteiro, "Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 6, pp. 1013–1026, Jun. 2008.
[2]. Y.-H. Ho, C.-U. Lei, H.-K. Kwan, and N. Wong, "Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications," IEEE Explore,pp.119-124, 2008.
[3]. Dempster and M. Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 42, no. 9, pp. 569–577, Sep. 1995.
[4]. H. Nguyen and A. Chatterjee, "Number-splitting with shift-and-adddecomposition for power and hardware optimization in linear DSPsynthesis," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8,no. 4, pp. 419–424, Aug. 2000.
[5]. Y. Voronenko and M. Püschel, "Multiplierless multiple constant multiplication," ACM Trans. Algor., vol. 3, no. 2, pp. 1–39, May 2007..

Paper Type : Research Paper
Title : Low power and area efficient Parallel chein search Architecture
Country : India
Authors : I.Kanaka Durgamma || K.Murthy Raju
: 10.9790/4200-0705015361     logo

ABSTRACT: The short horizontal Bose-chaudhuri-Hocquenghem (BCH) Chien search for signs of a new power-saving(CS) structure is proposed. For syndrome-based decoding, CS plays an important role in identifying the areas of error, but incurs a huge waste of exhaustive computation power consumption. The proposed architecture, the process of searching for the binary representation of the matrix is decomposed in two steps. This is neither new low power architecture for parallel CS provided. By reducing access to the second stage of the conventional CS to achieve significant power savings is decomposed in two steps. Error operate under the same ownership, the less energy the size of the CS in the construction sector in different configurations, and error correction capability of.......

Keywords: Bose-Chaudhuri- Hocquenghem (BCH) codes, ChienSearch (CS), low power,two step approach,modified booth encoding.

[1]. Y. Lee, H. Yoo, and I.-C. Park, "High-throughput and low-complexity BCH architecture for solid- state drives," IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 5, pp. 1183–1187, May 2014.
[2]. Y. Lin, C. Yang, C. Hsu, H. Chang, and C. Lee, "A MPCN-based parallel architecture in BCH decoder for NAND Flash memory devices," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 10, pp. 682– 686,Oct. 2011.
[3]. Y. Lee, H. Yoo, and I.-C. Park, "Low-complexity parallel Chien search structure using two-dimensional optimization," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 8, pp. 522–526, Aug. 2011.
[4]. J. Cho and W. Sung, "Strength-reduced parallel Chien search architecture for strong BCH codes," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 5, pp. 427–431, May 2008.
[5]. S. Wong, C. Chen, and Q. M. Wu, "Low power Chien search for BCH decoder using RT-level power management," IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 2, pp. 338–341, Feb. 2011...

Paper Type : Research Paper
Title : High Gain Amplifier Design for Switched-Capacitor Circuit Applications
Country : India
Authors : Pragati Sheel || Dr. Rajesh Mehra
: 10.9790/4200-0705016268     logo

ABSTRACT: In early decades, CMOS technology made its way into analog circuit design through discrete systems comprised of Switched-Capacitor circuits. Robust amplifier designs made it suitable for multiple applications. Few of these amplifier designs are implemented in this paper to meet the requirements of switched-capacitor integrator circuitries. One of the designs is a Two-Stage OP Amp and another one is Folded Cascode OP amp. Both the designed OP Amps are analyzed and tested for providing optimum Switched-Capacitor performance requirements. In accordance with this design strategy, both the proposed OP amps are optimized with design rules of 0.18μm CMOS technology. Small signal analysis is done in order to achieve the required design parameters.

Keywords: Two-Stage amplifier, Folded Cascode amplifier, Miller Compensation, Slew Rate, DC gain, Phase Margin.

[1] R. E. Vallee and E. I. El-Masry, "A very high-frequency CMOS complementary folded-cascode amplifier," IEEE Journal of Solid-State Circuits, Vol. 29, pp. 130–133, February 1994.
[2] Falk Roewer and Ulrich Kleine, "A Novel Class of Complementary Folded-Cascode Opamps for Low Voltage," IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1080-1083, August 2002.
[3] Behzad Razavi, "The Switched-Capacitor Integrator," IEEE Solid-State Circuits Magazine, pp. 9-11, Winter 2017.
[4] B. Grebene, "Bipolar and MOS Analog Integrated Circuit Design," Hoboken, NJ: Wiley Interscience, 2003.

Paper Type : Research Paper
Title : High Speed and Cost Effective Root Raised Cosine Filter using Distributed Arithmetic Algorithm
Country : India
Authors : Priyanka Agrawal || Dr. Rajesh Mehra
: 10.9790/4200-0705016973     logo

ABSTRACT: Intersymbol interference in wireless communication system is considered to be a major problematic area. Root-Raised Cosine (RRC) filters are used to overcome this issue. In this paper RRC filter using DA algorithm is designed and implemented. DA or Distributed Arithmetic replaces the conventional multiplier design with Look-up tables (LUTs) for typical implementation of FPGAs. The proposed design of Root-Raised Cosine (RRC) filter is implemented and stimulated using MATLAB and Xilinx ISE environment. Virtex-2-XC2V3000 target FPGA is used to synthesize the proposed design. The design implemented and synthesized is operating at a frequency improvement of 47.9% in comparison to existing frequency to provide effective solution to the existing problems.

Keywords: Distributed Arithmetic Algorithm, FPGA,ISI, Raised Cosine.

[1] Indranil Hatai, Indrajit Chakrabarti and Swapna Banerjee, "An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC," IEEE Transactions On Very Large Scale Integration Systems , Vol. 23, No. 6, pp. 1150-1154, June 2015 .
[2] P. K. Meher, S. Chandrasekaran, and A. Amira, "FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic," IEEE Transactions on Signal Processing, Vol. 56, No. 7, pp. 3009–3017, July 2008.

[3] K.-H. Chen and T.-D. Chieueh, "A Low-Power Digit-Based Reconfigurable FIR Filter," IEEE Transactions on Circuits and Systems- II, Express Briefs, Vol. 53, No. 8, pp. 617–621, August 2006.
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[5] Y. J. Yu and Y. C. Lim, "Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpressions Space," Circuits Systems, Signal Processing, Vol. 29. No. 1, pp. 65–80, June 2010..

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